Victor has done a tremendous job, both at creating EDA Playground and at explaining Verilog. I'm an electronics hobbyist who is just starting out with Verilog, in the hope of programming CPLD and FPGAs in the future. This is probably the best Verilog tutorial all over the Internet. Thanks a lot!
Comment from Connor Zaleski: This is super helpful and way way way better at explaining how to use this stuff by going step by step compared to the way my lectures seem to be. Also EDA playground seems like a great online program i can't believe our professors made us install quartus II. Thanks for the help and please don't stop doing these tutorials! Verilog Tutorial 5 -- Ripple Carry Full Adder
6000 views no comments? damn. This is super helpful and way way way better at explaining how to use this stuff by going step by step compared to the way my lectures seem to be. Also EDA playground seems like a great online program i can't believe our professors made us install quartus II. Thanks for the help and please don't stop doing these tutorials!
dude...I had to install Quartus II for my verilog adder program too and then I thought....what are the chances that he goes to the same school as me! I looked at the roster on angel just out of curiousity and there you were, in my class with narayanan lol
designbulk Haha ironically I found the video through google, then i noticed the link. So let's just pretend the world is as small as you initially thought.
Only tutorial so far that I've seen go step by step, and only tutorial that I've seen show how to actually initialize modules created before, inside other modules.
Karen Grace Victor Hi Karen, Victor has done a good job, hasn't he? This is Matthew Taylor. I work for a company called Doulos - we are an independent training company and have recently bought EDA Playground. There are various kinds of adder as well as ripple carry adders: you might want to google "carry look ahead" and "carry select" adders. Adder design is a tradeoff between area and speed: a ripple carry adder is small, but slow; other adders are quicker, but bigger. A ripple carry adder is slow, because the carry chain propagates through every stage. Look at the diagram Victor shows 45 seconds into the video - the carry chain propagates though all four bits of the adder. With a 64-bit adder, it would have to propagate through all 64 bits. So, generally in logic design, meeting timing constraints is the first priority and reducing area the second. So, if a ripple carry adder is fast enough, that would be used. If not, some other quicker, but bigger design is necessary. So, there isn't really a simple answer to your question: a ripple carry adder would be often chosen if it is fast enough. Chips I have designed generally didn't have fast clocks or wide data busses, so ripple carry adders were usually good enough. Cheers, Matthew
Sir , I am getting this error mentioned below. Finding VCD file... No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?
On the above example? Or on a different one? If on a different one, have you added those lines ("$dumpfile("dump.vcd"); $dumpvars;") to an initial block in the testbench? If so, please post the URL so I can have a look at it.
It would be easier if you could post a URL. However, here are 3 reasons why you mihgt not be seeing a plot: 1) you haven't checked the 'Open EPWave after run' check box 2) your Verilog/SV code doesn't include '$dumpfile("dump.vcd"); $dumpvars;'' 3) your simulation runs for more than 1 minute, so times out, so there will be no VCD file
Everything is fine sir I followed your tutorial but I am not getting the plot even after adding the dumpfile and var commands. And even I have checked EPWave after run. May be its my fault in writing. Once rsolved I will let u know. Thankyou sir
