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Video 74: Cache Coherence Example (cont.), CS/ECE 3810 Computer Organization 

Rajeev Balasubramonian
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This is the University of Utah's undergraduate course on Computer Organization. Instructor: Rajeev Balasubramonian.
This video describes a bus-based snooping cache coherence protocol to support a multiprocessor system. This is part 2 of a detailed example.

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7 окт 2024

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Комментарии : 8   
@krishnakumarshetti9334
@krishnakumarshetti9334 3 года назад
One of the best explanations on cache snooping. Thanks so much, Prof. Rajeev!
@omarshawqi5766
@omarshawqi5766 4 года назад
Incredibly well explained video - thank you!
@VikramReddyAnapana
@VikramReddyAnapana 10 месяцев назад
Thank you so much.
@arjithabhumanyu4110
@arjithabhumanyu4110 3 года назад
Thank you very much sir!. The teaching was very nice and I understood it very well .Thank you so much sir!
@vinaykornapalli7977
@vinaykornapalli7977 5 лет назад
Best video on snoopy protocol
@sugee98
@sugee98 3 года назад
what happens is you've a heterogeneous multicore system with one processing element (say a DSP, for example) that has caches but doesn't participate in the MSI/MESI/MOESI protocol. I presume a read request will cause it to get he correct data from either main memory or another cache. But what if it wishes to modify that location and has, say write back cache). How do the other processing elements know it's been modified? Must the DSP do something in software to alert the other PEs? Excellent tutorial - the best I've seen in fact!
@tousifmt_
@tousifmt_ 4 года назад
Awesome! thanks :)
@chelseaethiohighlights1971
@chelseaethiohighlights1971 Год назад
Thank you! excuse me, would you provide slide for us?
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