WHY SETUP AND HOLD TIMES EXIST? | STA-2 | Static Timing Analysis

Подписаться 4 тыс.

Просмотров 61 тыс.

50% 1

Hello,
Welcome to The Rising Edge!
I am Yash and this is the second part of Static Timing Analysis.
In this video, you will learn about the reason for the existence of Setup and Hold Times by understanding the internal structures and working of the D-latch and Flip-Flop with a brief introduction to the transmission gate.
Part 1(Introduction to Setup and Hold Times): • INTRODUCTION TO SETUP ...
Part 3(How the Hold Time can be NEGATIVE): • HOLD TIME CAN BE NEGAT...
Part 4(Setup Analysis and Maximum Clock Frequency): • SETUP ANALYSIS | MAXIM...
Part 5 (Hod Analysis): • HOLD ANALYSIS | STA - ...
Part 6 (STA Interview Problem): • STA INTERVIEW QUESTION...
Complete STA Playlist: • Static Timing Analysis
Stay tuned for the complete series, keep learning, and All the Best for your placement preparation.
#STA #Setup #Hold #StaticTimingAnalysis #SetupViolation #HoldViolation #SetupAndHoldTimes #FlipFlop #DigitalElectronics #PlacementPreparation
Song: Ikson - Spring (Vlog No Copyright Music)
Music promoted by Vlog No Copyright Music.
Video Link: • Ikson - Spring (Vlog N...

Опубликовано:

7 сен 2024

Ссылка:

Скачать:

Готовим ссылку...

Добавить в:

Мой плейлист

Посмотреть позже

Комментарии : 75

@anjaliagrawal4269 4 года назад

Your concepts are very clear and your attempt to make them understandable for others is praiseworthy. Good work👌

@RISHABHSINGH-uk3tm 4 года назад

Aapne engineering Safal Kardi humaari ..Samajh aa gya ache se sir

@therisingedge 4 года назад

This is my only goal. To help you guys. Keep supporting😉

@zoom0819 4 года назад

You have explained so clearly! Please post more such content

@therisingedge 4 года назад

Sure, more content on the way!!

@haricoolty 4 года назад

Sir ji aap great ho. Apki videos ne pass krwa dia . Thank u sirji 💥

@therisingedge 4 года назад

😄😄

@shreyakumari5350 4 года назад

I will watch all your videos..Things now appear so simple. Thank you so much !

@therisingedge 4 года назад

Happy to hear that!

@jothis3953 3 года назад

The explanation is crystal clear in very less amount of time. Waiting for more related videos. Thank you.

@therisingedge 3 года назад

Thank you so much Jothi, more videos coming soon.

@jothis3953 3 года назад

@@therisingedge waiting to watch

@himanikumar7979 4 года назад

Sab samjh aa gya sir. Thank you!

@therisingedge 4 года назад

That's great😀

@lorforlinux 4 года назад

Bhau maza aagaya 😮 flawless animation and very clear explanation. Keep it up yaara 👌

@nitdawg007 Месяц назад

Thank you for clear and concise explanation.

@shivambhati3388 4 года назад

Thoroughly explained 😃🙂

@akshitajain9964 4 года назад

Very creative and informative!

@ashokanbalan 4 года назад

Good job Yash. Excellent presentation.

@therisingedge 3 года назад

Thanks Ashok!!

@kollasivaramakrishna6732 Месяц назад

bro this playlist is gold

@b80thatiyashwanth53 3 года назад

Woww thanks a lot..Such a beautiful explaination made such typical topic a piece of cake... ❤️❤️

@therisingedge 3 года назад

Glad you liked it!!

@souravgoyal3338 2 года назад

PERFECT EXPLANATION

@harishannadata8268 3 года назад

Great presentation. Looking forward for more!!!

@therisingedge 3 года назад

Thank you Harish, next video coming soon!!

@saibhuvan30 2 года назад

I really loved your way of explanation and Please do more such concepts in VLSI

@sanhorizon777 Год назад

Wow this really gave me the concept I was looking for.

@suprbhakumari7919 3 года назад

very clear explaination.....please upload more videos.....they are really helpful

@therisingedge 3 года назад

Thank you, I will

@Manikumar-gt9ov 4 месяца назад

Wow...great clarity and explanation

@vikramadithya9597 5 месяцев назад

Can you please explain concepts on Power related also. Thanks for the video really informative.

@ramanakunduru4726 3 года назад

😎Nice Explanation Bro.... 🔥

@therisingedge 2 года назад

Thank you 🙂

@nithyashree5327 6 месяцев назад

Thanks for giving us this explanation❤

@prabhasiva659 10 месяцев назад

Your concept is good but we all that setup time is checked at capture of the flop and hold is checked at launch edge . can you relative this statement with your concept so that it will bit clear. any way super explanation ....

@cowbig8342 5 месяцев назад

Very very clear,a great explain

@praneethbogavilli5199 3 года назад

Good explanation. Waiting for a lot more vidoes

@therisingedge 3 года назад

Sure 👍

@loyal8060 Год назад

thank you so much bro, this is the concise explanation.

@anishaagarwal9192 4 года назад

Going great

@therisingedge 4 года назад

Thanks😄

@dont_care-x 2 года назад

thanks for making it easily understandable. Great work

@varsha6330 2 месяца назад

Thank You 🙏

@thatguy6442 2 года назад

I found Gold. Thanks Yash

@VLSI260 2 месяца назад

After d and before q in that's diagram they added extra inverters...what is the use of that ..if we want delay then we can use buffer itself also na

@gauravkaushal1037 3 года назад

Really great video, just a small query, The time that it takes after the positive edge of clock for the input to propagate from node X(where the value was retained) through Y to the slave part and hence the output, is that the clk2Q delay? And can I think of hold time in this way as the time it takes for the negative level sensitive gates to switch off?

@therisingedge 3 года назад

Hi Gaurav, thanks for your feedback and the query. Your understanding of the clk2Q delay is correct. And for the hold time, it is partially correct. First of all, the transmission gates are edge sensitive (level sensitive are latches) and I think you meant the gate number 1 that is turning off at the positive edge. Actually the hold time is determined by 2 different delays and this is just one of them. I have talked about them in the next video (STA-3). I hope that after watching that, it will be more clear to you. And still, if any doubt remain, kindly let me know🙂

@alterguy4327 3 года назад

It took 5 years to understand the topic clearly

@bhumikachaudhari5332 Год назад

Thanks a lot! Very helpful video.

@srinivas8030 Год назад

You have to add the clock to Q delay in this video for better. understanding

@alhasan5017 Год назад

Thank you so much

@therisingedge Год назад

You're most welcome

@tomoishandsome 2 года назад

excellent explanation!!

@ranabasit6046 2 года назад

Awesome bro...keep it up

@Awakened_Pot 3 месяца назад

why are inverters required in internal latches?

@alterguy4327 3 года назад

Thanks a lot

@saravananm92 7 месяцев назад

I am missing to understand, how metastability comes in here. The video does not explain, possibility of meta-stability. Its note a state of incorrect data, but voltage levels are such that , its nondeterministic. I guess there is a transient characteristics playing a role.

@tramontz2998 Год назад

Very good!

@sumiranbhasin1325 4 года назад

Thank you so much sirji. Please provide some questions too sir

@therisingedge 4 года назад

We'll do lot of problems, don't worry.

@RishuKumar016 3 года назад

Great video and very informative. Can you please make a video on Transmission gates also and in the meanwhile can you share any resource from where I can study it?

@therisingedge 3 года назад

Thanks Rishu, will consider your request. And for the resources, I actually use my own notes that I have made while preparing for the placements. I did not followed any particular resource, but looked online for whatever I could find and study everything available until things made sense.

@aditijain4351 4 года назад

Very good 👌👌

@goldenera1752 2 года назад

great bhiaya

@sanyamjain8225 3 года назад

I have a doubt.. Why are inverters there in internal structure of latch..I mean If we remove all the three inverters..then also it is working as a D-Latch. Please explain

@palakmishra2867 3 года назад

Great!!

@srinivas8030 Год назад

It was a very nice explanation. but, at 5:18 won't the output from flip flop would be ~X which is not expected from a DFF but with a TFF. please look into this.

@srinivas8030 Год назад

Got clarified there was a, not gate just after the signal was passed.

@srinivas8030 Год назад

I mean X is itself ~D