I'm having systemverilog code and inside it I have instantiated sub blocks which are also written in system verilog but when I try to use config view, it shows view to use only (which i would keep as external HDL view) for top level and not for the sublocks which are instantiated in the blocks of top level. What should I do so that I can get sub blocks there as well so that I can keep it's view to use as external HDL view
Thank you Sir😊 vy=Gm1*vx*(1/sc)=Gm1*(vx/sc)...(1) Therefoe ix=-io=Gm2*(-vy),ix=Gm2vy..(2) Substituting equation (1) into (2) ix=Gm2*Gm1*(vx/sc),vx/ix=sc/Gm1Gm2 So sc/Gm1Gm2=sL L=c/Gm1*Gm2....answer
When tuner provides the various impedance to PA output, Pout is measured at 50ohm ( for example, Spectrum analyzer). How we know insertion loss from tuner input to 50ohm Pout measurement point under a specific tuner input impedance in order to calibrate out that insertion loss ?
@@hardikjain-brb atan(1) = 45, atan(0.5) = 26, atan(0) = 0, atan(-0.5) = -26, atan(-1) = -45). atan is bound between -90 deg and 90 deg for input from -inf to inf.
Hi, could you please upload or share privately EMX simulation of the transformer? or anything that details out EMX simulation? I am also using 22FDX-PLUS.
sir, I have a module that I have created with the help of Mosfet but now I want to plot the resistance of my entire module from the input port but here I am using the sp parameter method to get this plot while using the sp parameter i am applying pulse input as my module resistance changes with the number of pulses applied to it so I want to plot the real-time resistance of my module as it changes with time as it is a function of the number of pulses applied so with sp parameter I am unable to get this plot can you suggest any method where I could plot this
Hi Professor, many thanks for your video! I am wondering do we need to change the differential port impedance to 100ohm and common mode port impedance to 25ohm for this evaluation? In this way, we can get correlated results as the 4 port evaluation using the conventional equation such as SDD11=0.5*(S11+S33-S13-S31). Thanks!
Hi Professor. Thanks for your videos. They are really helpful and advanced. Could you please send the link of the video about transformer layout and EMX simulation? It would be appreciable.
The DC simulation is just based on the device model, but does not include estimates of metal capacitance due to layout parasitics. You can add a few more terms (e.g., Coverlap, Cjs, etc.) to get a closer approximation, but the safest bet is to just use the SP.
The susceptance is linearly increasing with frequency, and the value in the plot is the correct value at the offset. Hence, we should not add the pss frequency to it. You can verify by setting the PSP frequency range to absolute and sweeping from frf +/- offset (e.g., 4.6GHz to 6.6GHz in this case). The result will be the same, albeit there will not be a divide by 0 in the middle of the range.