The susceptance is linearly increasing with frequency, and the value in the plot is the correct value at the offset. Hence, we should not add the pss frequency to it. You can verify by setting the PSP frequency range to absolute and sweeping from frf +/- offset (e.g., 4.6GHz to 6.6GHz in this case). The result will be the same, albeit there will not be a divide by 0 in the middle of the range.
The DC simulation is just based on the device model, but does not include estimates of metal capacitance due to layout parasitics. You can add a few more terms (e.g., Coverlap, Cjs, etc.) to get a closer approximation, but the safest bet is to just use the SP.
