Thanks a lot sir

as w\l is 4:1 that means k = 4 so for nmos it should be r/k = r/4 right ?

OMG, super easy to understand, really appreciate it sir. Thanks for your explanation!

Bless on milk of you mother

Explained very clearly, thank you

I loved the video, could you upload a video where a typical exam is solved? For example: Given the layout of the figure, it is requested: a) Bar diagram. b) Diagram with transistor symbols. c) Circuit operation table indicating, for all possible combinations of its inputs, the state of the transistors, conducting network and its equivalent resistance, logic value at the exit. Indicate the expression of the logical function performed by the circuit. d) Assuming that a capacitance of 0.01pF is connected to the output, find the maximum delay produced by the gate and for what type of transition it occurs. Data: Rp = 3kΩ, Rn = 1kΩ.? ......

excellent explanation 😊😊

thanks!

So unhelpful

How many times have you apologised here man 🤣

Made up voice is funny 🤣

thanks for helping

Thank you so much for this video! It helps me a lot!

Im confused about 1:13, how does activity work. Isnt activity #switches/cycle, you said #switches/cycle is '2' so activity is '2'. How does 1/2 come from

Wrong

Thank you. I understood the concept very easily.

Thank you so much

This video still shows up on my recommended after graduating 3 years ago lol

nice explanation and like your voice too :)

where did the resistance of D PMOS go ?

Can you make this kind of video? Your videos are really great.

your voice reminded me the announcers in clubs

Thank u sir, but can you help me in solving such circuit

Great!

SIR from which book/resource did u learn this? I want more questions for practice! I have an exam to pass on VLSI Design

You are a lifesaver.

What if the trees are symmetrical then which path i have to take

Hey great video!! But may I ask: what if there is a parallel RC circuit connected to the voltage input?

thanks sir

Thank you for the video. Great narration. I have one question: How can you find value of k for nand or nor gate with the help of unit inverter size?

Thank you very much for this lecture! This helped me a lot for my IC design learning. :D

Thanks brother it is good lecture for delay method

Gosh this dude's voice is so cool

You saved me!!!!!!

i lo veit thank u so much

should it be 2r/4 at 7:15?

Hello, I'm Cassey Miller. I would like to do the morning announcements.

from 2019 thank you

First non-indian guy that can help my dumb ass

ooh thanks a lot

Dude has a golden voice !

lmao y'all needa chill with the math xD we're here to learn about ee!

thanks for the clear and concise video!

Your math blows my mind.

correct me if im wrong sir. from the pmos logic you found, you just can do the opposite for the nmos. is it applicable for all circuit if we only just opposite the pmos to get the nmos? thanks in advance sir.

Fantastic video, keep the channel onnn

Thanks a lot br9

You didn't explain the theory behind this. What you did is nothing but some calculation. How ridiculous!

Thanks a lot Sir, Secondly your voice is so cool.

Really a good explanation