I loved the video, could you upload a video where a typical exam is solved? For example: Given the layout of the figure, it is requested: a) Bar diagram. b) Diagram with transistor symbols. c) Circuit operation table indicating, for all possible combinations of its inputs, the state of the transistors, conducting network and its equivalent resistance, logic value at the exit. Indicate the expression of the logical function performed by the circuit. d) Assuming that a capacitance of 0.01pF is connected to the output, find the maximum delay produced by the gate and for what type of transition it occurs. Data: Rp = 3kΩ, Rn = 1kΩ.? ......
left? All the transistors in the upside are PMOS and all transistors in the downside are NMOS because the circuit was building using a complementary logic with Pull Up (PMOS transistors) and Pull Down (NMOS transistors).
correct me if im wrong sir. from the pmos logic you found, you just can do the opposite for the nmos. is it applicable for all circuit if we only just opposite the pmos to get the nmos? thanks in advance sir.
