I have a question: the faults discussed in this video seem like they don't appear at the same time, can ATPG and signature analyzer cover these multiple faults?
I have an intuitive understanding of why CLBs with inertial delays might block glitches with widths smaller than the inertial-delay width. The way I look at it is, if the inertial-delay time width is narrower than the glitch width, the sampling time will not even register the glitch as valid data. Is this a correct understanding? Also, is there a more quantitative explanation or resource to understand this further?
hello sir, first of all thank you for your huge efforts for making these videos and making it available for free for students seeking knowledge. I've a doubt about why storage node is at high impedence( at 8:45 ) if it is between curtoff transistors M5 and gate of M3, also previously also u mentioned in 4 transistor DRAM, while storing, Q node is high impedence node , dynamically high impedence node bcoz M1 is cutoff and M5 is cutoff , can you please elaborate on this?
so in your example function, if I want to take care of both dynamic hazard and static hazard (0->1->0 and 1->0->1) I need to multiply the specific problematic term in F like you said to fix the dynamic hazard (let's denote it now as F_tilde) and in addition I need to multiply F_tilde with the term that fix the 0 static hazard and then add the term that fix the 1 static hazard? so all in all we will get that F_fixed = F_tilde * (0 static hazard fix term) + (1 static hazard fix term)?
He just starts to introduce a Wallace Tree multiplier and immediately make two 'improvements.' It just adds confusion. Should stick to a simple example first, then note the improvements.
Hello There, Thank you for the explanation Sir. I am having a bit of an issue while simulating the Read Mode of a 6T SRAM Cell. So, I can successfully write the value into the Cell and check if they are retained when I put the Cell in Standby Mode (WL = 0). However, For the Read Mode, what I do is I pass Pulse signal of VDD to both BL and BL' for about 1.5 microseconds and then keep it low. Then, I try to turn on the WL at 2 microseconds but what ends up happening is that both Q and Q' values are same which oscillate between 0.268 and 0.832 V. So, Should I actually Use Capacitors in the Circuit when using Read Mode so that the Capacitors can be pre-charged?
Thank you for your video. I always found it boring when I needed to read an explanation about the Wallace tree before. Therefore, I gave up before making an understanding of it.
Couple questions. * When computing the setup and CQ times, shouldn't we take into account the charging time of the capacitor? Or is this implicitly part of the tI's and tT's? * At 9:21 you mention that the requirements on the 1--1 and 0--0 overlap are more stringent than in static CMOS, and hence racing is more of an issue. But is it really that stringent? Roughly speaking, you'd think that the overlap time is roughly the delay time tI of a single inverter, right? * In the series of RC's in 10:54 onwards, why are they all connected? Wouldn't the transmission gates be closed alternatingly?
Thank you for the wonderful lectures. I have a question about the cascaded network in 4:28 onwards. The PUN appear to receive an inverter clock signal. But would it not have been simpler to simply swap the tail nMOS and the head pMOS for a pMOS and nMOS respectively, and just give it an un-inverted clk?
I think the way it works is that the DL gives a good idea of the number of defective chips in a sample size. While it is usually expressed in ppm as per industry standards, doesn't mean that is what we get from the expression of DL. For example, if the DL is 0.05% (according to the expression at 7:22), then this can also be expressed as 500 ppm.
Thanks for the refresher. It is interesting to note that the final circuit was essentially a mux. Which if you are using a mux for clocking, latch en, or set/clr that you have a potentially for glitches on that line.
