Compute Express Link (CXL) is a new breakthrough high-speed CPU interconnect that enables a high-speed, efficient performance between the CPU and platform enhancements and workload accelerators.
Industry leaders Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel Corporation and Microsoft have teamed up to form an open industry standard group to develop technical specifications that facilitate breakthrough performance for emerging usage models while supporting an open ecosystem for data center accelerators and other high-speed enhancements.
How can be the credits exchange mechanism work without LLCRD flit in CXL 3.0? I mean which flit should carry credit information after INIT.Pram Flit being sent.
Will these Micron memory expansion cards be available for Workstations platforms as well, like the Threadripper and Threadripper Pro? Or will there only be support for the Epic 9004 series? If there will be workstation support, are there plans for these cards being available as PCIe5 x16 slot variant add-in boards? With Intel Optane gone, I really hope CXL and Micron will include support for Workstation users as well.
Why do you think the CXL devices' cache size should be around 1MB? I'm curious about this because there are many GPUs that have a cache larger than 1MB
I wonder if CXL 2.0 would be able to be used to create a virtual machine that runs a single kernel that runs on all hardware as though it were one giant system. Not that I can think of a use case for this, it is just fascinating.
Thanks for the great video. I have a few questions about the video. In the case of Multiple Logical Device (MLD), one CXL Memory Node is likely to consist of 1 ~ 4 channels. Is the host assigned to each channel? Or, if this memory node is E3.S form factor, there will be 20 or 40 DRAM packages, are the hosts allocated in units of packages?
It seems the fabric manager manages system memory for all those hosts. In this case, the fabric manager has higher exception level than hypervisors. What exactly is this piece of SW?
It will be either be either a kernel module in the Host OS of a host (exception level = 0) like device drivers, or (for some CXL-compliant devices) implemented in hardware itself. The spec does not specify this, so it is left to the implementer. This is what I think, pls refer to spec to confirm.
