Demonstration of a CXL Interconnect on a FPGA-based Design - Rambus 

This video demonstrates CXL.mem read/write accesses to Host-managed Device Memory (HDM) between an Intel Host CPU and the Rambus CXL 2.0 Device Controller implemented in FPGA. The demonstration setup features Intel’s Pre-Production Xeon processor as a host, connected to an FPGA board instantiating Rambus’ CXL 2.0 Controller and CXL.mem test design.