Hello! I have an interview question, that I could not answer. There is high speed data coming in the fpga, how do you make sure all 8 bits are arriving at the same time?
Is it safe to say this particular project doesn’t consume any fpga resources at all? The output of P&R states no Logic Cells were used. So when you say “physical wires” connect the push buttons to the LEDs (via the FPGA pins) those wires aren’t a limited resource in the FPGA?
I just learnt these K-Maps, and don't believe I'll use them ever again, but they were useful for myself as a supplement to Boolean Algebra merely as a learning tool. In retrospect, I believe it was a necessary evil in the learning experience as another way of looking at it all. Naturaly, me being me, I couldn't stop at four input variables and had to dive into three dimensional K-Maps just because I simply wanted to know wtf was going on and why they'd be used! I believe in covering everything that assists me in the learning journey and having a firm foundation in all of this knowledge, but don't believe in spending too much time on a topic these days with the software we already have available. I think the problem stems from the 1960's when this was extremely valid and super important when all done by hand (Apollo Space Program). But these days universities need to catch up and move with the times and focus more on FPGA software training.
Hi! I:m really interested in getting started with FPGAs, and your channel looks promising. I:m just concerned the channel is coming to a close (not your fault! life happens and changes!) Do you have any plans to continue the channel or tutorials with the NANDLand Go Board?
Russel you are one of the best teachers I've ever read a book from (I finished it already). I'm a computer scientist at heart and I'm trying to get some hobby projects at first done and then want to transition into HFT. What further would you recommend me to try ?
Hi, i have a question, and i need your assistance. In a system, we make transfer with single port sram through spi protocol instead of transfering directly. Why? Many thánks
The best reference for digital timing is Sarah and David Harris' book "Digital Design and Computer Architecture" published by MK. The concept was clearly well explained in the book. The authors summarized and presented the subject very well.
FYI for 5/14/24, I'm still seeing subscription on Lattice's website for the iCE40 LP/HX/LM. I can't get the software to download either. I can't find the free license request page where it used to be. I'm still investigating though.
That is a great speech and very helpful for my next interview. But at 8:14 you said that DRAM was much faster than SRAM ? I think that is SRAM faster than DRAM ? Is it right ?
"Getting rid of metastability" - to be exactly: never, but you can reduce the probability to extremely unprobable (probability reduces by a factor by each FF stage), see also MTBF. Or to never cross clock domains of asynchronous clocks🙃
hello. and in your first lesson on the site ("Tutorial: Your First FPGA Program: An LED Blinker. Part 1: Design of VHDL or Verilog"), where do you connect the frequency output? could you tell us more about how you perform frequency division in this example.
