Example Interview Questions for a job in FPGA, VHDL, Verilog 

Thanks Doug Demuro of Embedded Systems

80% of the questions we covered in the last month and a half (sophomore year) in EE! Thanks for giving us the insight on what to look for and to keep on the tip of the tongue

These videos (and also your site) are extremely helpful. Just had several RTL design interviews the past week and they asked similar questions, so thanks so much man!

Best channel about learning in depth FPGA's Ive seen this far, thanks for all your con tent!

Using this to study for an RTL design internship interview in 2 days. Ever since I started watching your videos 5 months ago, I've fallen in love with FPGA design. Thanks for all you have done for me!

I knew most of the answers to these, but I always flop on interviews because I get tripped up on terminology. This video has been extremely helpful in giving concise answers for an interview format. Thank you!

Wow, a lot of useful material here. I'm not planning on interviewing for any digital logic design jobs in the near future. For me, this information serves as a list of interesting topics to study in order to begin learning about this field.

"Pretend like you're interviewing with me for your job, pause the video, give your answer to me. I'm not going to hear it obviously, we're not there yet with the internet but.. maybe some day". Haha, looks like we're at that day

I know about zero of these questions today, but it's great to have a good study guide. :)

Thank you a great introduction to FPGA I have a lot of discrete logic family experience mostly the 74 ABC families and some 4000 series (I got as far as treating them as analogue parts). I was surprised that I actually new the answers plus more detailed knowledge about how the digital blocks worked and what they are used for.

Thank you for your job! people like you inspire me to self-development

Great video, I have an interview coming up and it's nice to have a bunch of the topics I need to review in one place

I have been writing Verilog Code since at least 1994. I finished my MSEE in 1990. I have now been coding Verilog and Matlab for almost 30 years. Its very good that you made this Video. Good questions too. I wish you add more content - one common area would be 1. Clock domain crossings - in Verilog. 2. FIFO design with Grey coded counters in Verilog - Cliff Cummings - 1994 3. AXI-4 streaming Interface - which requires 4 signals. 4. AXI-4 Slave design.

Excellent and very useful discussion - I am impressed

GREAT VIDEO that summarizes very important info

I think that SRAM is faster than DRAM, and both flip flop and latch can have clock, the difference between them is that the output flip flop happens when the clock is going up or going down, meaning in the transition from up to down or from down to up ( 0 to 1 or 1 to 0 ) however in latch the output happens when the clock is up or down depending on the design of the latch

Awesome video. Great reminder of my college VHDL courses.

It was really useful to hear it in English. Thanks!

Great video... I have a tech interview in couple days. This gave me some confidence.

This is actually pretty good. Thanks. Great videos.

Mixed up things a little while talking about mealy and moore state machines. It's the output which depend either on the state and the input (Mealy) or only on the state (Moore). You were talking about state transitions, which depend on both variants on state and input. Maybe add a comment to the video to not confuse some newbies watching :-) Besides, great video! :-) Liked it.

I graduated recently and decided I wanted to work with fpgas after some experience with them during an internship, just after applying for a graduate role I watched this video and used your site to prepare for the interview and I'm happy to say it paid off and I got the job! Thank you very much for helping me achieve my goal of becoming an fpga engineer

Visited first time on this channel....Loved the question very informative

been listening to this vid on repeat all morning before my phone interview. thanks nand man

This is really nice. Good questions and I learned new things today. But At 7:50. Are you sure DRAM is faster than SRAM ? 1. SRAM uses multiple CMOS transistors to store a bit(typically 6-8 CMOS FET's) while DRAM is made up uses single transistor plus a capacitor. So memory cell of SRAM occupies more area than memory cell of DRAM. DRAM is thus more dense and can fit more memory bits in same areas as SRAM cell. 2. However, DRAM needs to periodically refresh (hence dynamic and not continuous power supply) the charge on the capacitors of its memory cell which tends to leak with time while SRAM cells remember their logic due to cross-coupling(feedback) and continuous power supply from VDD/VSS power rails (which makes it power hungry). 3. Data can be read from SRAM at lower latency (order or more) and higher bandwidth (several orders) compared to DRAM. So SRAMs are faster than DRAM. 4. SRAM is used for very small (KB to few MB) fast on-chip L1/L2/L3 instruction and data caches on cpu's/gpus or or scratch pad memory in embedded socs while DRAM (GBs to TB) is used off chip to store high amounts of data. 5. SRAM per bit is more expensive in terms of area, power, and money compared to DRAM so SRAM is only used in small sizes (on chip or off chip) and to store data whose access time is critical to speed.DRAM us used when higher capacity is needed but speed of access is not important.

Appreciate the video. I had an interview for digital design (with spacex) even though I'm a computer engineer. The questions that got me are the following: how do do know cdc data is ready when using dpram? explain some timing constraint experience how familiar are you with making build scripts (in vivado, libero, quartus, etc.) explain a fpga design you have been the lead of (schematic, worst case analysis, timing analysis, embedded c, etc.) just wanted to give you an idea of what I see in the modern workspace. I always send co-ops to your videos. keep up the good work!

I got the job as a design verification engineer in the VLSI domain. Thanks to Nandland your video helped me to crack it.

I was always taught that the difference between Moore and Mealy was not about what state to go to next but more about the outputs at each state. In Mealy, the outputs are dependent on the current state and the inputs, but in Moore the outputs are only dependent on the current state only.

Thank you for your video! It is really helpful as I am preparing for my interview tomorrow for internship at FPGA company :)

Very helpful when you need to prepare an interview!

Great video man, thanks for sharing!

Awesome....time well spent here learning

I think the answer for the difference of latch and ff is ff is triggered by edges of signals, and latch is triggered by signals.

Thank you for sharing this awesome video.

Starts at 5:36 basically, great video

thank you so much for this excellent resource

very informative, you earned a sub. Thanks a lot

*This was so helpful thanks a lot. Who else is here in 2020*

So the flow in an FPGA is Synthesis-> Map and Place and Route. The Netlist at the time of mapping does not have the RC Interconnect information. But its very useful in terms of the DSP resources and LUT count and DFF usage and Block RAM usage. This is why doing a three part synthesis flow provides one information in a "timed " way compared to all in flow Synthesis flow. I commonly check the Map resources Table to see if the RTL is really using too many DSP resources and BRAM.

Synthesis tool - can be provided by an Independent CAD tool Vendor Such as Synopsys or Cadence. Commonly FPGA vendors can provide two options a). Their own tool like LSE for Lattice and b. third party tool e.g. Synopsys Synplicity. Occasionally a student can try to switch between two Synthesis tools in the same FPGA setup. But Xilinx Vivado will use its default tool and this is most recommended. when you switch tools sometimes you need to provide a different timing file - TCL script. Running an RTL code in two tools is not necessarily the smartest thing to do.

Thank you for great content!

"Melee machine!" HAHA, that's a good laugh. It's "Mealy", "melee" is a fight.

Appreciate the effort, you were helpful there sir...... But u look like doug demuro of electronics and i can't unsee it

Wonderful! Many thanks. :)

Bus arbitration and methods of arbiter operation might be an area where you wanna add questions. Such as what is the difference between round robin arbitration and priority coded arbitrations.

My background isn't electronics, so this is a very useful guide for highlighting my knowledge gaps. One question I have - is the assertion that DRAM is 'larger and faster' than SRAM correct? I always thought that SRAM was faster, due to the lack of need for refresh cycles which delay read/write, and use of directly driven flip flops, rather than gate capacitance to store the bits, hence it's use in cpu cache. As a software engineer, I find the whole topic of being able to design hardware at the HDL level of abstraction fascinating. It's high enough level to not require lots of phsical knowlege, yet low enough level to understand how it maps to real hardware (or rather how it could be mapped to real hardware, outside a clever device like an fpga).

Excellent Questions to learn. If you are an interviwer than I would never got the job, lol

That's very helpful...

Thank you for this video! I love having interview questions with Jim Halpert :D

I WISH YOU HAD A CHANNEL TEACHING FPGA FOR BEGINNERS. YOU ARE REALLY GOOD AT TEACHING. YOU CAN HAVE A CLASS ON TEACHING EVERYTHING ON FPGA'S . Like what is a FPGA ,real life examples of why a person would use one , what are all the pins for ,,how to program them and basic manufacture design of FPGA. I personally would be on that channel every single video...no one has that ...i have been checking for a while now. you are good are teaching

could you do a tutorial of DDR PCIE Ethernet or something like that? i think it is widely used and very helpful for me

“Name a few flip-flops”….uhh crocs and Birkenstock…. Hired!!!

its very helpfull video thank you:)

DRAM is not faster than SRAM because DRAM requires constant refresh to retain data and CPU cannot retrieve data from DRAM while it is being refreshed. In contrast, SRAM, since it's static, it can be accessed anytime without waiting. And because of the smaller size of SRAM, walking through the cache pages is much faster than the bigger DRAM.

Your video are so good and helpful. I appreciate that you made it! I have a question. I studied electronic engineering in university and got my masters degree in Korea but when I graduated I got a job as a software engineer and worked for 1 year. I moved to the US and I realized I want to start over my career as a FPGA engineer or anything related about that position. What do you recommand for me to study? Or for interview. It's been a long time i haven't studied about digital so I think I should start over all basic major knowledge and a small project by myself. Actually, I have no idea how to start a project in FPGA field if you can recommand it as well it will help me too. I have no experience any studying or interview in US. I will really appreciate your advice.

"Being wrong is most of being an engineer" Man .. you got it there 😁

I believe that Sram are much faster than SDRAM, nad main difference is that Dram is much more volatile than Sram so we need to refresh periodically but in sram its automatically refreshed as there is crossed couple inverters pull the data continuously with out recharging , and can also diffrentiated by the construction of these memory

Your answer to the difference between Latch and Flip-flop, Another more prominent interpretation is the Latch is level triggered and Flip-Flop is edge triggered.

That is a great speech and very helpful for my next interview. But at 8:14 you said that DRAM was much faster than SRAM ? I think that is SRAM faster than DRAM ? Is it right ?

hey awesome video.

I am a high school student trying to figure out some FPGA for ADC to RAM dump for a science fair project. Feel like ready for a job.

Thank u.. So much..

I like how after he asks a question, he goes 'yeah this is basic, if yo don't understand it..you better learn it' lol

Great video! Do you ship the GO-Board to Australia?

They should change the name to melee machines because of how confusing they can be to work with. Great video

it's helpful ,thx

I think there is a mistake on the question about moore and mealy FSM. I think the the main difference is the whether the output depends on the input or not, not next state.

I think the questions are reasonable, some answers are fine, but not all. Some answers are wrong enough to give you a bad outcome in an interview. Here are some corrections: q3: diff flop latch A better answer is the difference has to do with how the output gets updated. When a latch is open it is 'transparent.' Changes on the input D show up on the output Q (after some tprop). In a flop the output does not change until the flop is clocked. So changes on the input before the clock are not visible on Q. When a latch closes D will no longer effect Q, until the latch opens again. q4 choose an fpga FPGA's are _always_ slower and bigger than an equivalent std. cell design. It is fundamental to how FPGAs provide the re-programmable feature. E.g. a 14nm FPGA will achieve ~+500MHz in logic/processors, a 14nm std. cell design will achieve ~++2GHz, all other things being equal. This is because FPGAs implement some logic indirectly (luts, muxes, etc.) while std. cell designs implement logic directly (nand, nor, etc). This speed difference is the reason FPGAs have to provide hardened DSP blocks and the like to mitigate the performance degradation. The main points are: ASIC/std cell's are costly to manufacture, can not be changed without re-manufacture while FPGAs have a better cost model, can be iteratively designed and can be modified even in the field. i/o has nothing to do with fpga vs std. cell. high mem b/w requirements have nothing to do with fpga vs std cell tons of math operations, these are always as fast or faster, smaller, less power in a std cell design all the applications you mention are easier to implement in a std cell design than FPGA. q6 diff between sram dram You should skip this answer completely and go find your own. If you gave me this answer it tells me the candidate does not understand the difference. There is a difference between access time and bandwidth. DRAM is not faster than SRAM, do you see any cache tags or TLB's built from DRAM? Nope, all SRAM. All things being equal SRAM has more available bandwidth than DRAM due to refresh overhead and due to the row activation, column activation semantic required by the multiplexed address pins of DRAM. DRAM bit cells are fundamentally smaller (3 or 4T cells) than an SRAM bit cell (6 or 7T cells). That is why you need to refresh DRAM, it's charge will degrade, not SRAM. 3/4T makes DRAM great for bulk RAM. q9 what is meta-stability Again, good question but go find another source for the answer, using this answer will not help you. Anytime you violate the setup and or hold time of a flip flop you risk putting the flop output into a meta-stable state, i.e. it is not reliably a logic 0 or a logic 1. The flop's physical design determines how long it takes for the flop to stabilize. The signal source, internal or external, has nothing to do with the likelihood of inducing meta-stability. If the signal is asynchronous to the clock used by your flop there is a probability of inducing meta-stability. The risk of meta-stability is statistical, the more asynchronous the driving clock to the capture clock the more the risk of meta-stability. This is the reason dual flops are used to capture source asynchronous signals, including those crossing a clock domain. The dual flops reduce the probability of a meta-stable event to near infinitesimal. q16 clock crossing Fast vs slow is not the issue. Two clocks of the same frequency but not synchronously related still require meta-stable filtering techniques. q18 melee(sic) vs moore This is text book stuff, good question for junior people, if you are one you should have this exactly memorized: Mealy: outputs determined by current state and current inputs. Moore: outputs determined only by current state

"Getting rid of metastability" - to be exactly: never, but you can reduce the probability to extremely unprobable (probability reduces by a factor by each FF stage), see also MTBF. Or to never cross clock domains of asynchronous clocks🙃

I have a little bit confused in Q22. What is a DSP tile in FPGA? Can you give me a simple way to understand that? ^^ I hope I will get as soon as answer from you ^^

Even though these questions seem relevant, they are really like a university course exam. I'd never hire a candidate based on answers (on pretty simple) random questions. A minimum requirement today is a coding interview (and not just a typical FIR filter BS), and an actually good interview is of a problem-solving type. So giving a candidate a real life problem to think of possible implementation, to sketch a microarchitecture and to write some code example. Or find a problem in an existing design code example.

Great video! How much time do you expect the interviewee spend answering each question?

i think you made a mistake on the sram dram part. i thought sram is faster than dram because sram uses transistors primarily for storage rather than the capacitive storage that dram uses, which takes time to charge and discharge.

bawa yaar. phoda. Gori gori gori

Appreciate your help! I really needed something like this. But now I have couple of questions for you, 1- What companies, from your experience, can be good examples of a working environment in this field? 2- What do you exactly do in such a job? In boring details please..

Melee model :DD Btw thanks for the video :)

I used for in verilog to cycle through something. Not to duplicate it, so I don't know if that's valid.

Turns out I knew answers to most questions (except SERDES), though I made 0 FPGA designs... Probably time to create one.😸

at 19:24 DSP is to fast multiply accumulate operations? i'm not sure it i heard it correctly

thank youu

I thought synchronous meant that was timed with the rise or drop of the clock and a synchronous could have a clock from an external signal but was not in line with the timing...

I recently landed a job as an FPGA engineer. They asked pretty much the basics. However, I wasn't able to answer a couple of them. Could you help me with that? 1. Using IPs(microblaze), HDL wrapping and writing C programs using the Xilinx SDK vs Doing everything using VHDL from scratch to finish - Which method is more efficient in terms of timing, area, and resources? 2. Simulation looks good, synthesis and implementation look good, a bitstream is generated and FPGA is programmed. However, the FPGA doesn't function as per requirements. How do you go about debugging starting with your bitstream? I think these two questions are critical.

thankew

i am working on a fault injection system

There must be a lot more harder questions?

I want to become an fpga engineer. All I know is C and digital logic design basics. Kindly guide me.

Concept questions are more suitable for phone screening.

Granted I'm an EE student and likely won't be working with FPGA's when I graduate but these questions were a lot simpler than I expected, and I didn't like my FPGA course :P

Not an expert, but is DRAM really faster than SRAM? Would have guessed that it is the other way around....

haven't replied about how to prevent metastability

SRAM is faster,and the difference between f/f and latches we can say they both use clock but in case of latch it works as enable or disable and in case of f/f it is triggered.Correct me if I am wrong thank you

4:00 A melee machine beats the hell out of you lol

Can I join your patreon and choose the highest package available so you can teach me and clarify my doubts? 🙈 Damn you are good at teaching ! Please let me know if you would be able to do that 🙏🏻

I think you missed a very basic differences between SRAM and DRAM - DRMA need refresh, SRAM does not. This is significant because refreshing DRAM will tie up more clock cycles and FPGA complexity.

Thanks! Which of the FPGA companies do you think have a brighter future?

As someone who got into FPGAs just a few days ago, I can confidently say I will not be getting the job

very basic question. But not easy with new bie =))

The types of flipflops i remember now is D flipflop, SR Flipflop, T flipflop and JK flipflop.

I believe Q6 answer was quite wrong. Also, the mealy vs moore answer wasn't explained correctly.

Is this Doug DeMuro?!