It's amazing how many through-hole ICs are out there with so much power packed into them. I have a manual from 1983 full of these ICs. I think that year was the apex of such chips before microcontrollers would start creeping in. Thanks.
EXCELLENT information on using an old CD4046 in a Phased Lock Loop setup. I fully agree also, that this is a super simple look at setting up a PLL for educational and demonstrational purposes, however, as you clearly stated at the end of this video IMSAI Guy, there's quite a bit more involved in designing, let's say, an tunable RF modem Phase Locker. Really, really good stuff though sir. As always, you presented this in a way that I think anyone can grasp and even implement! Thank you for making this video IMSAI Guy! Fred
That was fascinating. Although I understand the principals of how a PLL works I've never actually had a look at the signals that are generated. Hopefully this is just part 1 of a PLL series of video's. Thank you, keep up the great work.
PLLs are so cool :) Prior to joining the service and getting training in satellite communications my experience had been mainly with radios that used multiple crystals to generate the frequencies for a superheterodyne transceiver. As we started learning about how the local oscillators and synthesizers worked in the satcom gear to generate the SHF frequencies from a lowly 10 MHz or 100 MHz reference by using multipliers and dividers all sorts of light bulbs went off. By having a programmable divider you now had flexibility over the operating frequency without having to get new crystals. Sadly, this spelled the end for places like Omaha Crystal where I used to be able to go and order a crystal of any frequency cut and have it ready in no time. As you noted, the basic design of PLLs is pretty straightforward, but they can get really complex and one of the engineers that works for me actually did her Ph.D on PLLs.
GREAT VIDEO!! (you've 501 thumb's up's right now). I can see soooo many applications I can this 4046 PLL chip for, with all you've shown other than (standard PLL apps) and greatly lower my IC-count. BTW: I like to think of the XOR as a 'controlled inverter'....with one input pin HIGH, the output inverts the other input, and follows it for one input LOW. THANKS MUCH!!!
This was cool to see the phase detector output rolling without a lock. I had forgotten about the XOR function of the phase comparator. The old TV sets just did an ORing with a double diode in the horizontal oscillator.
When I understand that. I'll consider myself no longer a noob. I know all the gates and the different algebra and stuff from reading old text books and playing with a cheap fpga. Haha
Works great with a sharp, relatively steady pulse wave. For fun, and excitement, feed complex waveforms in. Thank you for such a detailed and easy to grasp explanation. I'm coming at this curious about how this synthesizer module works. Now I want to learn about the various other comparator modes one could use.
you should lock the 555 on the scope, which is your unchaining reference. That would be more intuitive. Also, at first I thought you meant alignment of rising edge. But in the end it's "some" constant phase offset.
Thanks for the recommendation - I'll need to review some of my EE classes to get the most out of it, but it looks like what I need right now at work. Thanks!
Professor, This was a very nice introduction to phase loop locks. One thing I would like to see is how one would use this device. It seems like I've heard that phase loop locks are used for portable radios, but how does it become so important? Thanks for all you do to keep us learning!
Very well explained, thanks! I wish the college books could explain the operation first in simple words as you did before diving into the deeper theory.
How does the output voltage from the low pass filter correspond to the exact voltage which generates a wave of the same frequency as the timer? How does a 50% duty cycle correspond to the phase lock ? In a frequency synthesiser PLL we need the VCO to operate at different frequencies, how is that accomplished? Say for 50 MHz operation the input voltage to the VCO is 5 Volts, now due to some instability the frequency of the VCO drifts to say 50.5MHz, at that point does the PLL need to bring down the VCO voltage to bring down the frequency ? I guess so. That means the VCO voltage vs frequency curve has changed ? Would be great if there could be a follow up video on this.
I'd be interested in a video on the loop filter design criteria. I guess you need clean dc to control the VCO but too much would slow down the locking time.. Also most PLL circuits have an additional resistor in series with the filter capacitor. A down to earth discussion on these points would be very helpful.
So phase-locked loops don't actually cause the VCO to match the phase of the input signal?? I assumed at lock they'd be exactly in phase, but I guess not. I never could get my head around how they would cause that to happen, and I guess the answer is "because they don't." I remember reading about the CD4046 as a kid and thinking there was no way I'd ever understand how the hell these things worked. Yet, here I am, and I get it! Thanks for making this video!
can you tell me how to achieve low phase noise using PLL in GHz range ? ready made chips from AD and TI with integrated VCO give better phase noise only below 100k and can not give more than 128dbc/Hz 1MHz away from carrier...
I am missing something. In the signal flow diagram at about 15:00, why should the system "prefer" that the average of the XOR be at the halfway point? Is the frequency from the VCO inversely related to its voltage input?
the average 'match' of the XOR gate happens at a 90 degree phase shift between the two signals. it is easier to think about frequency only at first. if the frequency is too low then the average signal will be low and the VCO will speed up. if too high the VCO will slow down.
@@IMSAIGuy - Thanks for the reply. However, my question remains albeit somewhat altered. Why does the system "prefer" to lock in at 90 degree phase shift? As nearly as I understand, there is equivalent of an op-amp with negative feedback set to 0.5 to drive the VCO. At least that's where I think I am stuck.
@@IMSAIGuy Thanks. Your video explains the XOR concept as well. W2AEW's video does not close the loop with the XOR (Type 1) phase detector, but does with a Type II. I have looked at other videos and search references. I cannot find an explanation for the lock. One puzzle is that the voltage into the VCO from the LPF controls the frequency of the VCO output, but in both videos the desired reference frequency and the output frequency are shown from the start as being the same. This is a negative feedback system and it appears to me that critical elements for that negative feedback explanation are missing.
Drat. I didn't understand what happened at 17:33. Just because you take an average of a signal... How did something loco? Where did that average go? I would have liked to see the circuit at that point.
I bought one of the original "TI"-parts on easter-monday, for 0.46€ a single piece! (Pollin-Electronics ; Germanny) Want to make some "tests" and "experiments", too,... you are the "number one" again, ... ! But this doesn't matter! I bow my head to you. 73 de Markus ; db9pz
You show timings on a cro but you do not show actual exact connections and R and C values around the cd4046, so we have no idea what are you showing us
I'm sorry, but this was a terrible explanation. I know you meant well, but you shouldn't try to teach a subject that you don't really understand. Try doing some preparation first next time.
do a video and I will post it. maybe mine was too simple. I'd be curious what you think was terrible. the 4046 is just an xor gate and vco. not much for me to mess up.
@@IMSAIGuy People like this never have the ability to do better they just like to complain. I work for a famous Competitor of HP in the Spectrum Analyzer group and your explenation was excellent.
