Subscribed... thank you for delivering this with such energy and enthusiasm. I am a very low level electronics student (level 4/5) (distance learner) and have found much of the content so far very difficult to digest. You have really broken walls here for me. Best regards.
When you calculate the Max Intrinsic Gain of the CB stage, you forgot that as Rs increases, less and less voltage appears across the transistor. Your calculations should include the Rin / (Rin+Rs) term which shrinks as Rs increases, hence the actual intrinsic gain of gm ro.
The active load for a common emitter stage is somewhat strange. It's like connecting two current sources in series which is impossible in circuit theory. It'd make the circuit irregular wouldn't it? How can we still make this? How can we resolve this contradiction? Is it enough to assume that those two current sources have finite resistance?
What would happen if we would to change the Vbe of the top PNP transistor like Vbe of the lower NPN transistor in CASCODE, or have it with inverted phase? Would we get some benefit?
