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125N. Two transistor stages: cascade, folded cascade, active load, Darlington, current mirror 

Ali Hajimiri
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Analog Circuit Design (New 2019)
Professor Ali Hajimiri
California Institute of Technology (Caltech)
chic.caltech.edu/hajimiri/
© Copyright, Ali Hajimiri

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4 авг 2024

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Комментарии : 17   
@milindgoel405
@milindgoel405 2 года назад
20:30 headroom explained. 28:00 small signal model is same for PMOS and NMOS 38:00 Ideal current source , ideal voltage source 41:00 MOSfet ends
@tianmingguo8271
@tianmingguo8271 4 года назад
Thank you so much!!! Great lecture. I was reading Darlington and the current mirror from different textbooks. Your explanations are the best and easiest to understand.
@mortezaalavi
@mortezaalavi 5 лет назад
Yet another impressive lecture, Now it is time for 21-century microelectronics, RF, and linear circuit textbooks which coupled your multimedia lectures to your original textbooks.
@AliHajimiriChannel
@AliHajimiriChannel 5 лет назад
Thank you very much for your kind remark. I hope I have the time to develop it. Perhaps you can help me with that :-)
@mortezaalavi
@mortezaalavi 5 лет назад
Sure, My great pleasure, Always, and any time.
@clippotronics522
@clippotronics522 5 лет назад
this moment you messed up the exams at home university (other reasons ;D) and still so fascinated by this lecture. How can i get to the cal tech ??? :D :D
@abdulladeeb5515
@abdulladeeb5515 Год назад
More than fantastic... Your playing a sinfony ...
@SJayanth
@SJayanth 2 года назад
58:43 Sir, isn't the bottom transistor already acting as a current source. What is the need of an additional current source on the top? This way, we have to connect the drain of it to some Vref to setup the current. Or is it just that instead of a Vref connected to the drain, you directly chose an Iref current source in series? And very very thanks for the lectures. I bow down for passion of teaching and maintaining a great exciting environment in the class. I never thought or heard circuit Design as an art before you described it many times in the class, previously I thought "all the equations, techniques, mathematics is established, simulators are there. What new can I add? But, now I see room for contribution for the variety of needs a circuit or system can demand.
@maxq4515
@maxq4515 7 месяцев назад
There seems to be few mistakes in the calculation of the output resistances seen through the cascode stages. The expressions mentioned here are different from those derived in the last video.
@user-zl2vm3ez9s
@user-zl2vm3ez9s 4 года назад
Sir, the video helped me a lot. But it seems that there should be another part in this class, but the next video is another chapter. If there is following contents or this class was over?
@MrGyulaBacsi
@MrGyulaBacsi 2 года назад
At around 9:00 you're writing for the output resistance for the MOS cascode as r_o = r_o1 * ( 1 + gm_2 * r_o2 ) but it's actually r_o = r_o2 * ( 1 + gm_2 * r_o1 ) isn't it?
@royalabhishekarya3143
@royalabhishekarya3143 Год назад
Is it possible to simulate folded cascode current mirror in cadence?
@rtv1196
@rtv1196 2 года назад
So, what about gm of the Darlington pair?
@alpergirgin1
@alpergirgin1 4 года назад
nice shirt
@excitedbox5705
@excitedbox5705 4 года назад
How many cascodes do I need to get enough gain to read that tiny handwriting? :D
@coolwinder
@coolwinder 3 года назад
It's just dense with information! :)
@caleb7799
@caleb7799 11 месяцев назад
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