All universities in the entire world should just use Prof. Ali Hajimiri's videos to teach their students. 99.999% of teachers cannot possibly explain things better.
I'm "arrived" here from start of you playlist and I found this video the best one (I think it's for the large number of questions asked) . Thank you very much, this is the best electronics course on RU-vid... I continue the course now. P.S. there is a little error on time 46:11, It was indicated the Vout as the total gain
In the diff pair with active load (no current mirroring), the way it was drawn show that the active load is voltage biased using vbias, while in the common mode operation, this active load should have current of Iss/2, which is current biased. This is not going to work, since voltage biasing states that the current is K'(VDD-Vbias-Vth)^2 = Iss/2, and both Iss and Vbias are defined! What is the correct way of generating Vbias? Is it using the same tail current source, mirrored in other branch so that Vbias is something like VDD-VSG=VDD-sqrt(I/K') and we design K' such that there is no conflict?
You are right If you have two unequal current source in series, the voltage increase so as to bring them equal and one eventually ends up in linear region So one has to bias properly. But if I think about the current source, the vo,cm is defined by the the current itself.If the currents are not same vo,cm adjusts to keep the currents to iss/2 so channel length modulation may be an important parameter that you have to consider to think how the vo,cm is set. But yes you are right we must keep the current close to iss/2 to get max swing
I have a naive doubt, @44:20 when you flip the current direction by altering the sign. How can an NPN collector source current, won't they always sink currents? I understand I've got something wrong with the fact that this is small-signal analysis. Can this change in direction of the current be seen as follows? When we say negative in small signal, we mean a "drop" in the current (in the same direction), so at that output node, when the collector current of Q2 drops the collector current drawn by Q1 increases which is reflected on the output node on Q2, hence we don't lose the gain. TLDR; This change in sign and direction is not literal right?
Yes, it is literal. This very current he's talking about is the small signal one. It varies around a DC op point, so there is nothing wrong with the transistor. You have to remember the sum of both T1 and T2 current are always equal to that one he had choose, 1mA I think. Its been 4 months, had you got the answer?
In the circuit 14:00 , when there is a mismatch in the load resistors then in the calculation of Differential gain, how are considering the common point at Differential ground? Similarly, when you are calculating common mode gain in that circuit 14:00 how could you ensure that there is no current flowing from between two rails and you can apply open circuit between two rails to calculate common mode to differential mode conversation? Because the circuit is losing its symmetry
Hi Good question If Rc is changed by a small percentage, it is important to note that the differential ground is still valid as both the nmos are still in saturation or forward active for bjt Then since the current through the rm resistance is same if you consider the T model and hence the node has to be at differential ground However if the mismatch is at the bjt or nmos WL,vt etc then the gm of both the transistor are different and hence differential ground no longer applies.
@@rohitn1704 Thanks for your reply. So, you wanted to say the change of load resistor does not impact the current flowing through the rail. So, for Common Mode calculation same amount of current flows through both the rail even though load resistor has been changed and no interchange of current will happen at common point. So, the current has to go through individual Resistance attached with the Source terminal which is nothing but twice of the output resistence of the tail current source. Yes, your analysis is true in this case. But, what happened in the differential gain. You have said that it is valid for this also. So, if it is valid then we can apply Half Circuit concept here. But through half circuit we get different gain from different half circuit. Is it correct? Then, how is the differential ground concept true for this case?
@@ayanchatterjee3884 half circuit symetry is not valid Differential ground is If the same current flows through both the legs, then the drain voltage adjusts to make it equal. So there is no symmetry. If you think practically due to channel length modulation differential ground is also invalid so there will be slight change in the Vs but if we choose to neglect that we are still okay Same case as in ota where differential ground is still applied to keep output resistance ron || rop otherwise we have to consider degeneration.
