187N. Intro. to phase-locked loops (PLL) noise 

No Matter how many books you read, Prof. Hajimiri always comes up with a new explanation, even for a topic which is heavily lectured by lots of people

Great thanks for you great efforts Prof. Ali Hajimiri

LOVE to see U here， Prof Hajimiri

thank you very much for all your efforts, keep it up

it's really good to know the history behind these topics as well as the technical aspects. I've seen plans for double sideband QRP construction, is it a mode used at all today? I suppose you can tune SSB into either of the double sidebands?

The best PLL that I have ever heard. Mer 30 Ali ye gerami!

Thank you from north africa (Algeria)

Hi professor, I have a question, please... For frequency synthesizer/clock recovery scenarios (scenario 1 and scenario 2) where the VCO is noisier than the input, why the phase noise PSD of the VCO is flat (constant) up to the loop bandwidth? I thought it should be 1/f^2 (as open-loop VCO). I thought it should be similar to the phase noise PSD of the input. thanks

Dear Prof. Ali once again thank you very much for sharing your great classes! Also want to say sorry for missing out on your Webinar 1+1=3, but the time of the Webinar was 23:00 in the country I currently am :( Nevertheless looking forward to watch it when it is available at IEEE Solid-State Resource center next week hopefully :) Best Regards!

Dear Professor you're like a flower :)

Wow

Sir please refer any book for PLL

Very useful video, but my god, that equation formatting is the stuff of nightmares.

WHO CAN WRITE A NOTE?PLZ. Or me.

good fucking content

9:30 Tau_z should be Rz*Cp (and not 1 over Rz*Cp)