This is second installment of Band-gap video series. In this video three different architectures of band-gap circuit are considered. They include conventional architecture, current conveyor based architecture and Banba architecture.
Thanks for the very detailed explanation. It really helps me a lot. I cannot find a single book explains bandgap in such clear and easy-to-understand way!!! It saves me a lot of efforts to browse many related papers and painstakingly try to digest them.
I am using the circuit you showed at 8:49. I am getting an issue in transient simulation with that circuit. Initially my VDD is 0 and then when i ramp up my VDD, BG voltage is oscillating and i am unable to find where to put the compensation capacitor or how to solve it. Do you have ideas to solve that? I did put a startup circuit and have tried many topologies and played a lot with it. Nothing seems to solve the issue.
in Banba circuit, there is also another resistor equal to R2 from V1 node to ground. This will equalize currets going through each of the diodes. You have missed it in your picture.
Yes you are right. But I have omitted this resistor for the sake of simplicity. Even without that resistor a bandgap works reasonably well. But thanks for pointing it out.
I didn’t understand in last part, where ctat ptat currents are added through v2 node. Through R1 is vt ln N upon R1. That’s ptat but how current through R2 is ctat .? Is that because v1 and v2 is same so vbe 1 upon R2 is ctat
Hi, I have another question about the circuit at 9:44, how do I calculate the resistance R2? since I have seen in some places that the relationship is 10, but in others it is described with a formula, but I do see that it varies everywhere
A bigger N is good to minimise effects of amplifier offset and in general is a good thing. The drawbacks of large ratio are: more area, and since current is divided in many fingers, current in individual device becomes small. BJT models become inaccurate at small current values. A good rule of thumb is 10-100nA per BJT device. A large ratio also means that current in individual device (the branch with 1 device) becomes too large and secondary effects start to come into play. A good rule of thumb here would be 1-10uA. Most common ratios are 8, 16 and 24. 8 and 24 are particularly good for layout. Although maximum ratio that I have seen in a design is 100. If you have offset cancellation techniques implemented in your design then you can choose smaller ratios. Minimum that I have seen in a design is 1:7.
Not sure what you mean by current mirror self bias, but for a current mirror you would size it to have maximum length that you can assign and maximum overdrive that you can allow. Try to determine the maximum mismatch that you can tolerate and then increase length to achieve that.
@@analogsnippets In 9:25, It indicates that I adjust the length, but the width also doesn't? Let's say what advice or what suggestion would I give to adjust these two branches and that the currents coincide, since I have made variations and sometimes I have slightly different mirror voltages or currents, then there comes a time when I don't know whether to increase the widths, the length or the multiplicity of pmos or nmos
