Analog Snippets aims to create short, bit sized videos to help budding design engineers to ease into vast and complex field of Analogue design. Creators draw from years of experience of designing analogue circuits, mentoring new engineers and conducting job interviews. These videos target topics where creators found people struggling with the concepts. These videos should also help college students in understanding the analogue circuit design better and give some intuitive feel to the subject. These videos should also be helpful to someone trying to brush up the circuit design basics. Also, these videos should be great help in preparing for a job interview.
Thanks for your material. Always very clear, easy to understand and intuitive explanation. I have a question on iso nmos G/R connection, what if let it just floating instead of connecting it either sub or pgnd_bst. Thanks in advance.
Hi Sir May I know your thoughts about future of Analog IC design. which area in analog IC design will have more demand in future (like data converters, Analog AI chips, etc) What new analog IC’s do we need in 2026-2030 that we don’t have yet
It is really difficult to predict the future, especially in tech. But the demise of analog is being predicted since I joined the industry (that was 20yr ago). But rather than being extinct, analog engineers are in ever more demand. And I think that is going to be the case for the foreseeable future. One reason is that the supply is small, as more and more colleges and graduates are gravitating towards more fancy domains, e.g. AI. And it is rather difficult to automate analog due to its inherent complexity. Analog has also evolved, embracing increasingly more digital, making the system more complex. Power is going to be dominated by analog for a long time, although with a lot of digital thrown in. Sensors are going to remain analog due to the nature of inputs. High speed data converter will also be difficult to replace by all digital, and so is RF. If and as technology settles down (i.e., no more new technology) the foundation analog IPs would be first to go (bandgaps and basic building blocks). Anything that you need to only make once or twice in a new node. Then probably general purpose IPs e.g. LDOs, standard data converter and PLL. Custom IPs will remain for long time. But then it assumes that march of technology will stop, which may itself take some time. Then there could be new applications which will prolong life of analog. Analog compute, quantum computation, wearable health, EV, renewable energy. All these new domain will require custom design. Long story short, I am pretty confident that I will not be extinct when I retire.
@@analogsnippets Hi Sir, Thank you for your reply. I am into hardware design for past 12 years(not chip level,board level). Analog IC design is my passion. Now got an opportunity to do PhD in the same. May l know your thoughts about it
All is very nice, but there is one thing I couldn't understand: At first, we put a large capacitor parallel to the first amplifier such that its crossover point came on top of the second amplifier's pole. Then, we put a pole and a zero parallel to the first amplifier such thatthe resulting zero came on top of the second amplifier's pole. Which one of these is the dominant pole compensation?
❤ Thanks a lot Sir...Ive read many books+journals for SD ADC but, u explained in such a lucid way....Can U. Give more insight to how should we design Decimation Filter? Should We use a LPF at output to reduce noise? What is the role of Delay z^-1 block they r talking about in book ?? Why PSD of output is needed??
Hello, Thanks for the informative tutorials. I would like to ask for some clarifications about the start up with R-as a current source and no additional circuitry. Please refer: ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-783Itlm-pUs.htmlsi=Tqve3zdylIq7CtUR&t=627 Even if the Amplifier comes alive, my concern was that if the differential input is positive Vp > Vn,then the output of 5T OTA is held at ground level, resulting in stuck state.Vp > Vn may occur because of input referred offset of the Ampl. or perhaps during start up Vp rises faster than Vn (due to large diode cap at Vn, whereas only res at Vp). I will be grateful if you could share your thoughts on this. Thank you.
I want to oppose your layout choice regarding the common centroid. The best option in terms of common centroid would be one of the two: A B B A B A A B B A A B A B B A OR B A A B A B B A A B B A B A A B This is because your choice in the video has two different axes of symmetry (both in the x- and y-axis) for each matched device and thus does not preserve the rule of coincidence, meaning that the centroids of the matched devices should coincide. For more detail, I recommend the excellent book The Art Of Analog Layout by Alan Hastings. Nevertheless, I appreciate your videos and encourage you to continue the very good work! Thank you!
I observed comparing "sigma" ie Standard deviation with "delta" ie change in video 8...is this always correct to compare sigma with delta?(dimension are same) based on "video 8" sigma of beta equation is different from what isshowed in "video 9" ie In video 8 "Sigma of Beta" is equal to "Beta" times what is shown in video 9. Can you please clarify this ? Thank you
I have been adding tasks to xls sheet month wise and changing color once closed. I segregate mentoring and personal tasks with different color code. I carry the pending tasks to next month. It helps me recall all the tasks that I have accomplished during reviews.
That sounds like a good idea. I have tried something like that in the past, but after a while, I stopped doing that. May be I can give it a try again this year.
These are good methods. I can attest that the first one is effective as its longtime user. However, one needs to be selective on which one to "fire" as some easy-looking tasks can take more time than you had anticipated or, worse, can end up distracting you and killing your motivation to do the next more important task.
Please continue to the topic of minor loop compensation and answer the questions you have raised at the end of this video.. I have first encountered minor loop compensation in prof. roberge's lectures but could not understand an iota of it.. Your lectures, by contrast, are crystal clear...
Thank you for your feedback and glad to know that you found the video helpful. Yes, those questions are still in my mind. Hopefully, I will get back to them in 2024.
@@analogsnippets Actually I lied. Videos are not helpful.. They are extremely helpful... Heartfelt thanks for them 🙂 You have one guaranteed audience if you also do some programs on feedback in audio amplifiers.. I suspect the same methods might also have currency there..
12:30 In weak inversion, mismatch for both cases should be the same since sqrt(WL) for both cases are the same? Not sure why you said the 2nd device has to be 4 times?
Hi Sir l am a hardware design engineer with 11 year's of experience in analog hardware design (board level). May l know is it possible to move to analog IC design. I can see that there are some institution which provide course in analog IC design. May l know your thoughts
Your analog hardware experience should be very useful if you want to move into analog design. I guess the best route would be to move into any analog team in your own company. Analog design course would be useful if they are offering actual design projects. If you have tools available, then try designing any circuit yourself, e.g. a bandgap or an LDO. I would suggest that after that, you brush up your basics and start applying for openings. All the best.
@@analogsnippets Thank you sir.My current company doesn't have any analog ic design team.The institute l mentioned provides training using virtuso and will teach blocks like LDO ,Opamp,Bandgap etc.
Hi sir how current in the inductor gets negative or current direction get reversed?? I mean once current reach to zero it should stop there and again should charge in the positive direction but it go to the negative direction? Could you please explain
If one of the switches is on, then there will be a non-zero voltage across the inductor. So, according to v=L di/dt, the current will keep ramping (di/dt = v/L). For example, in the case of buck, if low side switch is on, then there is a negative voltage across the inductor. So, the inductor current will keep ramping with a negative slope (that is, it will keep ramping down), irrespective of the magnitude of the current. Hope this makes sense.
This is an extremely useful video.. I think in radio science inductors are a lost art. After watching this video, a lot of things about them become understandable...
I am using the circuit you showed at 8:49. I am getting an issue in transient simulation with that circuit. Initially my VDD is 0 and then when i ramp up my VDD, BG voltage is oscillating and i am unable to find where to put the compensation capacitor or how to solve it. Do you have ideas to solve that? I did put a startup circuit and have tried many topologies and played a lot with it. Nothing seems to solve the issue.
I'm a professor of A/D conversion at a local university and was really struggling to explain the sigma-delta converter to my students. This video and the park track example gave me a great method to teach it more intuitively! Thank you for this!
Nice video Saurabh. PFM is a powerful technique to enhance efficiency at light loads. However, in lots of applications fixed switching frequency (e.g. in RF) is desirable ---to correctly frequency plan and ensure harmonic frequency spurs do not land fall over intended signals. With PFM and pulse skipping, such control becomes difficult.
