You could've simplified the circuit a lot more by using Qa, Qb etc as the next flip flops clock and used a 2:1 MUX to select the output between Qa and Q'a and so based upon the select input M.
1)simply use a 2:1 mux and a common mode line as combinational ckt. 2) u can't get all possible combination in M,Q,&Q(bar) table because Q & Q( bar) are always complement of each other as u using jk(1,1 state)/T ff. 3) collect the output as Qa, Qb, Qc. when M=0 u'll get up counting & when m=1 u'll get down counting (in conventional way).
We can simply use XOR operation (M XOR Q). Lets say, for M=1 we want to do down counting and for M=0, we have to do Up counting. Then, clock of Q1=Q0 XOR M. when M=0, clock of Q1=Q0 XOR 0=Q0(which is the condition of up counting) and when M=1, Q1=Q0 XOR 1= Q0 COMPLIMENT (which is required condition for down Counting.
The use of XOR instead of AND + NOR gate (which is a 2 to 1 MUX) is logically correct. However, you need to consider loading at outputs of the flip flops, Using only Q output with XOR will have uneven loading and hence rise time will be different from fall time. This produces duty cycle != 50%. It can cause issues at higher clock frequencies.
It felt like this was rather incomplete, what was the output in this case? I am guessing if it were up counting it would be just "Y" for each bit, and " Y' " for down counting. Yet is there a way I can store a number in a counter and be able to both increment and decrement it according to my needs :D? (I feel like what you just did will do the job but still can't see it clearly) Thank you for putting all these videos for us.
My teacher used positive and negative edge triggering randomly and the circuit design is so confusing. Thank god I saw ur playlist. It began filling in the holes that were left by my teacher.
there won't be a case when there is 1 1 on both the outputs because we are feeding 1 1 as the input to the flip flop and the output generated by this combination gives the previous state which can't be 1 1. The truth table that is creating this confusion shows merely the possibilities but it doesn't necessarily mean that there should be 1 1 as the output.
so i built this circuit in multisim, and it turn out that when m is 0, you have a down counter (the bits ripple through to make 111 from 000 initially) and and when it's 1, you have an up counter. I made this with XOR gates instead of the AND/OR logic you implemented but the function was the same. just wanted to clarify if anyone else comes across this. Thanks for your videos, I watch all of them religiously
There is a problem with this circuit, sir. If the output of the combination circuit is high when the mode is changed, the next flip flop will register that as a falling edge and change state. This design can only switch modes reliably while in the 000 state. In other words, you cannot count up 0-1-2-3 then switch modes and count down 3-2-1-0. That mode change will trigger flip flops B and C and change state, and the resulting number will be 5. This is fine, if that is the intended behavior, but you may want to disclose that.
For an up ripple counter it knows it always increment, it only needs a signal that tells it when to. For this up/down ripple counter, it is not really ripple since it has a clk. It always change value at the posedge of clk, and it only needs to know whether to increment or decrement, which is still one signal. To design an async up/down ripple counter it needs two signals: when to change, and whether to increment or decrement. Because of setup time, constraint, it is impossible to work with only one signal. We either use delay unit which brings tons of physical requirements, or use two counters.
another way to do this one is to use 3 xors at the outputs than 2 xors at the clocks: use output_a as (m xor Qa), output_b as (m xor Qb) and output_c as (m xor Qc) - this comes with advantage of not having clock cycle shifted by 1 (see previous video)
I feel using a 2:1 MUX between all pairs of consecutive flip flops would've been better, taking control input M as select line and inputs being Q and Q' of the previous flip flop and the output being fed as clock to the next flip flop.
Well, actually you do not need to add Q's complement to table since it will be always opposite of Q. When you do it with only M and Q you can use just a XOR gate as combinational circuit.
one more question :- a sequential machine produces an output 1 only when exactly two 0's are followed by 1 or exactly two 1's are followed by 0. Determine the reduced state table of the machine.
Hello , thank you so much for this ! i was wondering though , what about the outputs , shouldnt we make a line going from Q a,b,c so we can show the result of the counting ?
The Truth table u made in the beginning to figure out the circuit structure to be inserted in between flipflops had # columns M Q and Q'. and u have considered the entry where both Q and Q' is 1. which is impossible because Q and Q' can not be 1 at a time. But it dint affect ur final circuit because Q=Q'=1 is a dont care condition and u can count them as 1 in ur k-map. But u should rectify that
Sir in the M Q and Q' table, there are two cases (namely 011 and 111) when Q = Q'.... But then Sir how is that possible and allowed in a digital circuit to occur ?
In finding the relation for Q and M why did we consider one of the inputs like 0,0,0 and 0,1,1 .I mean if we consider Q and Q' they are not supposed to be same na ?
for up counting we need to feed QA_bar as clk to next flop right so if it should happen at m=0 then function would be M_bar.QA_bar + M.QA . So Finally we need to use M xnor QA
Design a 4-bit ripple up-down counter with two control bits C and D. The circuit counts up when the control variable C is logic ‘HIGH’ and counts down when C is logic ‘LOW’. The circuit will work only if 𝐷=1 and remains unchanged if 𝐷=0 ...????
As the outputs of flip flop are complement of each other .... Why did you consider the case where q and it's complement is equal..While making combinational for.
Hi guys, as positive feedback, I have tested your circuit, but both mode perform a down counting only. For 2 BITS counter both mode count: 11, 10, 01 and 00. I think you should revise your circuit. For 2 BITS up/down counter, please look carefully that output Q of 1st T flip-flop must trigg the clock Pulse for the second flip-flop since this is a typical of asynchronous counter. Then, the output Q and Q' of first FF must be chosen using 2 to 1 mux then we OR both and take the output of OR gate as one of it output bit itself (Verify MSB or LSB. Do the same step for the second FF, third FF and fourth FF for 4 bit up/down counter modulo 16 from 0 to 15. Thank you.
here , when M is 1the output of combinational circuit is Q bar but you didn't give any information about the output of flipflop. without knowing about output of flipflop how can we judge that the counting is up or down ?
