Carry Look Ahead Adder (CLA) Explained 

For more information, check Digital Electronics (Playlist): ru-vid.com/group/PLwjK_iyK4LLBC_so3odA64E2MLgIRKafl Timestamps: 0:00 Limitation of Ripple Carry Adder 2:00 Carry Generation and Carry Propagation logic in CLA 4:40 Carry Look Ahead logic for 4-bit Adder 10:28 Delay Comparison between Ripple Carry Adder and Carry Look Ahead Adder 13:30 Limitations of Carry Look Ahead Adder 14:52 16-bit Adder using 4-bit CLA blocks

I'm honestly so so so grateful to this channel and this person! You not just made me score good in exams but made me understand the deep meaning of concepts. Thank you very much, truly grateful to you!

This tutorial explains it better than any other one I have watched. Thank you so much for the tutorial.

my soul left my body after trying to analyse the last circuit design

Complexity explained in the flow of water, hats off sir.

Everything is fully explained. Thank you!

Very Perfect Explanation for the CLA

10:28 Gx and Px should be switched in the Carry Look Ahead Logic Circuit block.

So smoothly presented! Thank you!

I am literally in love with you now I can finish my homework

Straight to point explanation... Go ahead sir🥳

This was an amazing explanation👍

Very good tutorial man, thanks for the video

Always enjoying your posts

Thank you very much, i finally understand the gate logic behind CLA adders. Been trying to learn the gates to make a faster binary adder in a game.

Beautifully explained.

Fantastic explanation, thanks!

Amazing video! Thank you so much

I hope you can explain the last two-level carry-lookahead.

Wonderful explaination....🔥🔥🔥

the last circuit for CLA is bit complicated to understand for me can you please explain it

Is it not supposed to be 3 gate delays, because it waits for 3 parallel gates before it's passed to the final gate for implementation. Like the 3 parallel gates are delaying the calculation in the final gate.

I'm confused cuz on Harris&Harris textbook, Propagation is A+B(i.e. A or B) but not A xor B, why is that?

Sir can you explain me about gate delay . Why it is 1 gate delay & 2 gate delay ?

time 10:23 in the video there is mistake that is you took P as carry insted of sum. specifically in P1, P2,.....

in 4 bit cla block diagram there is a mistake in naming of P and G

whats about the delay in the last clag ?

So synchronous carry is actually carry lookahead…

I am having very informative time to listen your lecture but I cannot lie that I haven't noticed your intonation. Are u indian robot? I am sorry If this offends you. I love your contents!!

Which adder is currently implemented in the industry?

My village is so back

awesome