For more information, check these related videos on Adder and Subtractor: 1) Half Adder and Full adder ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-5XbRIVWFRIw.html 2) Ripple Carry Adder ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-b70ZQwci5sY.html 3) Half Subtractor and Full Subtractor ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-lqN8xLTtdaA.html
00:11 Designing a 4-bit subtractor circuit 02:57 Performing subtraction using an adder circuit with 2's complement 05:28 Performing subtraction using the adder circuit 08:01 Performing subtraction using a modified adder circuit. 10:42 XOR gate can be used for both addition and subtraction 13:23 Binary addition and subtraction using XOR gates and adder circuit 15:59 Performing subtraction using 2's complement form 18:21 The adder circuit can be used for addition and subtraction
It is just like a private lesson, a teacher teaches me topics I have no idea about detaily, thank you very much for saving me:))And also thanx for the subtitles sometimes because of the accent I cannot understand some parts and other than that when i speed up the video thanks to the subtitles i do not miss anything
sir your inglish is very gut. i want to take classes from you. i have a dream of securing full marks in inglish. when you say "The output of xor" hits different.❤
Great explanation sir. What it the output from the And gate is 0, since A>B. We don't want it to do the 2's complement of B again and then add since A>B. How would the system know it's to stop if A>B.
If A > B, And if you are performing A - B, then you will get carry at the output. That means Co = 1. So, here since it is applied through invert to the AND gate, so the output of the AND gate will be 0. That means the output of the second ADDER is same as the output of the first adder. ( since XOR gate won't invert the S3, S2, S1 and S0 ouptuts of the first adder, and C0 for second adder will also be 0). I hope, it will clear your doubt.
@@ALLABOUTELECTRONICSThank you sir, I had to go back and look at it again, A0-A3 is 0, so it won't change the value of the 1st adder as you said the carry out it's applied through invert to AND gate.
Hi, I have tried to make the same the circuit on the circuit verse but upon doing the addition of 1111 and 1000 bits the carry out of the second 4bit adder is not giving the 1 bit as the output carry, so, do we need to need to get the output of the carry or borrow bit from the 1st 4bit adder module ?
I have a question, why does the 2's complement checker does not work when you add two negative numbers? Ex. -2-1 = 1110 + 1111 = 11101. So the most significant bit, which is 1, is inverted and then it goes through a AND gate with the CTR value, but the result ends up being 0 (0 * 1) . Even though the result is in 2's complement form. PLS HELP, I have a project related to this. Thank you!
This 2's complement checker here only deals with unsigned integers (positive numbers only). We are only subtracting ONE unsigned integer from the other unsigned integer. They cannot both be negative, since the circuit can only convert one of them to its 2's complement representation. However, the 2's complement checker here is also not 100% correct, it fails to account for subtraction by zero, which will never output a carry bit and thus, the checker would mark the result as a 2's complement number when it isn't. What you are doing is adding two SIGNED integers. The inputs and outputs are already guaranteed to be in 2's complement, so you don't need a checker there. (You might need a checker to detect overflows (+ve + +ve = -ve) and underflows (-ve + -ve = +ve) which you can do by comparing the MSBs of the two inputs and the output)
Your explaination was awesome. But i have a doubt sir , if we add two 4 bits which results to get a 5 bit output then the carry output atlast will be not shown by this method because we use not gate and multiply with ctr. How to overcome this problem?
If you closely observe, C4 output is still available. Of course, the same signal is given to NOT gate and to AND gate. But in case, if the carry is generated then it will be available. Whether it is valid carry or not, that depends on the output of the AND gate. I hope, it will clear your doubt.
what would change if the operation was like -3 +4 , thats like my problem right now is how to represent the negative number , i know that there is 1's & 2's complement representation and there is a sign magnitude representation but in the implantation on the circuit how will the gate recognize if the most significant bit is a sign
sir i have one doubt in this, here we use bin0 as our control pin, as when bin0 = 0 , then the circuit perform addition, and when bin 0 = 1; the cicuit perform addition, but if we have our bin = 1 in addition case i.e if there is alreay a carry in , then we can't perform addition here.. it will do subtraction in that case. please clear this doubt
you need to connect the Cin input with CTR input only for the first block (The Least significant Block). Suppose you are cascading multiple such blocks then you can directly connect Cout of one block to Cin of the next block. In the next block, you don't need to connect CTR with Cin. You can check it manually or you can also simulate the same thing. I hope you got what I mean to say. If you still have any doubt then let me know here.
Yes, It will work. But it is better to use the same arithmetic blocks for each bit. (rather than a little different arithmetic block/without inverter for LSB)
at 20:05 suppose I want to add 1001+1000 using the Adder/Subtractor circuit, The final result is 10001. In this case CTR=0 , as a result output of AND gate will be 0. So the sum result from the first 4 bit RCA will be 0001. Since AND output is 0, Cin at Second RCA will be 0 and all A3A2A1A0 of second 4bit RCA is 0 added with B3B2B1B0 which is same as B3B2B1B0 of first RCA (since AND output=0). The final sum output of second RCA will be now 0001 but Cout of second RCA is 0 ( all A3A2A1A0 of second RCA is grounded) . But we know the final result is 10001. how this carry can be missed out in second RCA. . Kindly help.
@@ALLABOUTELECTRONICS I know it's for 4-bit unsigned numbers. The circuit only solves for when B is either positive or negative. What if A was either positive or negative too. We can have A-B, A+B and also -A-B. The question is for the scenario where -A-B needs to be solved for sir. Thank you.
for the question (10-12) the answer would be 11110 when we calculate simply without using any circuit but in the final circuit while performing (10-12) the result concluded by (4-bit adder-2): s3s2s1s0 is 1100 with sign 1. while the answer should be 11110. no true form or 2s complement form. the answer should be 11110 which was given by single circuit, then why add the second?! please clearify.
Since we are doing the subtraction in binary, 2s complement is preferred one. One might argue for 1s complement method instead of 2s complement, but in 1s complement representation we have two different representations for '0', which is convenient for implementation. I hope, it will clear your doubt.
But in calculator we don't have two display for input. We have only one display so we add serially like at first input 3 then input 2 and we get output 5. How we can design this type of circuit which will take input serially like real life calculator and we get output using memory flip flop and logic gate. I didn't find the answer how our real life calculator is working and saving the input in memory then add it to another and produces output.
The truth table for adder subtractor is already covered in the previous videos. For more information, you can check this video. ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-5XbRIVWFRIw.htmlsi=gNYYW1Ai8k_lLvwW
