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Clock Design (Part 3) 

VLSI Physical Design
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20 окт 2024

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Комментарии : 10   
@TheYasaswy
@TheYasaswy 4 года назад
Hi Team, This video is not working. Can you look into this and fix it?
@shilpisrivastava5836
@shilpisrivastava5836 3 года назад
Hi, Can you please check. This video is not working.
@praveenkumarberla
@praveenkumarberla 3 года назад
Go to:. nptel.ac.in/courses/106/105/106105161/ Select lecture no. 26, select window - videos and then u can watch
@kundankumar-ll8in
@kundankumar-ll8in 3 года назад
@@praveenkumarberla wanha bhi nhi chal rha h
@ratneshsinghai4629
@ratneshsinghai4629 2 года назад
Why they have added 4ns to data path delay,it should be added to clock path delay?
@akashashok5478
@akashashok5478 Год назад
I think it comes in the data path for the second flip flop as explained in the calculation of propagation delay for a flip flop earlier in the lecture
@gyaneshjha8870
@gyaneshjha8870 4 года назад
is this clock path delay same as that of the hold time delay.
@gauravgautam2603
@gauravgautam2603 4 года назад
No. Clock path delay is different.
@tinystepswithmomg
@tinystepswithmomg 7 лет назад
how to calculate clock path delay ?
@gauravgautam2603
@gauravgautam2603 4 года назад
Total time taken by clock from source point to FF clk node point
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