Construction & Working of Enhancement-Type MOSFET (Part 2) 

No seriously man I saw ur vid in 1.5x both part 1 and 2 and understood what my teacher took 1 hour to explain and me not understanding a single word. Thanks man keep up the good work!!!!!

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In case 2, As Vds is increased, the reverse biasing also increases( Drain terminal connected to n-type well and also given positive voltage). As reversing biasing increases, the depletion region increases, and because the depletion region increases, there is lesser and lesser flow of charges.

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The most exciting part of the video is that the Kirchhoff laws are marked in the subtitles, which is the key to understanding the second half of the video.---from China

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Case 2 not clear 😫😫

At last!! Thank you!

Thanks for this easy explanation.

For case 2...before Vds was increased there was a forward bias due to Vgs .by increasing Vds you reduce the effect of the forward bias since the drain terminal is connected to the +ve terminal hence depletion layer increases

Channel tutorial is really awesome.........

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sir I m not understanding case 2 and3

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when vgd becomes more positve how can drain become less positive(case2)

Amazing. Thank you 😊😊

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When drain becomes more positive the potential difference near the gate source region becomes less positive . So the attraction force becomes less .But toward source terminal it's grounded so gate source voltage difference is high enough to attract the minority carries from bulk

Case 3: Think of it as a line segment with 3 points: S------G------D (similar to the MOSFET) If we need S+G to overcome the VT threshold, then we could say, we need S+G to get to D. With this understood, then we could say, S+G = G+D are of equal length. Now, D+S is a total length of the line segment and remember, the line segment is broken in 2 equal parts: S-----G & G-----D. If you understood my 2nd sentence, then we could also say S-----G---VT---D because we need the length of S+G to get over the threshold (VT) to D. If the line segment is 2 equal parts, then: S---VT---G & G---VT---D... so if we took away S+G, then we are left with G--VT--D, thus VGD = VT. I hope this brought some clarity.

helping me a lot.....

Need Lecturers like you in college

For people having doubts in case 2, think of it as a reverse biasing a P-N junction.

Hi.. thanks for the excellent video. Can you tell me which book you have followed in making this video? I need some more explanation about a few things. Thanks

Excellent

Sir in case 3 when Vds=Vgd-Vt Then Vgd=Vt Then why the current is not equal to zero as width of channel near drain is zero

Thank you sir

You saved my semester...

Whem Vds = 0 there will be no Id right? Since both the source and drain are at same potential?

sir ...plz upload lecture on classes of amplifiers

Please talk more on pinchoff region and body effect.

What happens when you have too many biasing voltages plz explain about that point

What do you mean by uncovering of ions? Which ions? Which electrons? Those what are bound with Intrinsic semiconductor (Si or Ge)? Or Doping material (B, Al)???

Sir I did not get the CASE 2 and CASE 3. Sir please do make a new video to explain in detailed way...I saw the video 3-4 times but still did not understand what are you trying explain in those two cases..Plzzz help us in those two.....

Sir in case 2 when u say drain is becoming more positive the width of the channel reduce and depletion will increase why.?.... when it is positive then width will increase and depletion will also increase because of increase in reverse bias potential ..... sir plzz clear this out

Thanks!

Shouldn't the Id current flow from Drain to source?

Life saviour

In case 01 at 10:04 after applying kvl I am getting Vg + Vgs - Vds - Vd = 0 . Sir can you please check it why ?

sir in this video i think the biasing will be of opposite polarity.... pls confirm this.....is it right?

Sir we connect source and body terminals because we do not want too many biasing sources.So why do what is the special reason of connecting source to body and not drain to body?Can we connect drain terminal instead of source terminal to the body.

How can the depletion layer be equal when one of them is forward biased and the other one is reverse?

how can current flow in case 1 when we make vds =0 there should be potential difference across the terminals for flow of current may be both channel widths would be equal but there wont be any conduction

Sir a question arise in mind that if G has more positive then P type material having minority's charge carrier will flow toward Sio2 then due to less content of e why are not recombination between hole and e then how could e generated on other side of G

"SIGNIFICANT CURRENT FLOW" what does this significant mean?? nA or mA or uA??

I didn't get Case 1. Why would the voltage between D and S equal zero? That actually means that there's no current flowing from Source to Drain. It's kind of paradox to me. On one side the channel is opened (which means that the current is moving from Source to Drain) and on the other side Uds=0 (no current flows from Source to Drain).

Sir i have one doubt mosfet is symentrical device but y we are cal it as source and drain

For case 2 think of a normal diode... Now apply +I've terminal of battery on n side and -ive on p side as in case 2 in drain.... Now think if it's reverse bias or forward I.e reverse biased so deplition layer increase....

Sir you have told that we try have only one biasing source. But you use two source at Vgs and Vds

why we are finding conditions for Vgd ?? i didnt get it??

Why the channel width is decreased only near drain for CASE 3

At 14.58 When you are telling about the thing that when drain becomes more positive, less positive charge and hence less electron interaction. But since drain is becoming more positive,shoukd the force of attraction increase and so channel width increase and depletion region reduce?

sir please give an lecture on transistor as an oscillator.

Hi sir In case 2, channel width is getting reduced. What about current flow in that condition whether the current increase or reduce? Because in drain char. when we are increasing vds current also increase. How can current flow increase when channel width is reduced. Pls clear this sir.

sir i didn't got case-2. If drain is becoming more positive than why did drain region gets less positive voltage than source region?. please answer it sir

Vgd influences if the depletion layer is uniform or not.

I have a doubt. In case 1 you said that we will keep Vds as 0. That means drain and source are short circuited. If drain and source are short circuited, why should be there any current flow through the channel??

Good

sir please upload Amplifier tutorial...

why does V(ds) even matter, shouldn't the channel width be totally dependent on V(gs)??

In the three case why you have not consider case of V(DS)

can anyone explain me 10:4 Vg-Vgs+vds=VD i want to know Vg-Vgs+vds+vd = 0 KVL says total voltage sum = 0

why does channel become narrow at drain ? and not at source.

Case 2 and 3

Does his explanation imply that Vds>Vgs in case 2??

how drain current would change with increase in Vds

I like u, sir.

if drain is becoming more positive and we also giving positive potential to th gate..then ..both ..positive voltages.will combine and will make ..drain side more positive ..so the channel ..must be wider at the drain end..buy in video ..you have told just opposite ..that channel is narrow at ..drain end ..why ..is my explanation is wrong . ..pls explain me..!

case 2 and case 3 is not clear to me... help me out

Don't get case-3..plz help

how did u apply KVL to Open Loop ?

Small doubt why don't you use white background if you can use it, then all the writings are clearly visible

Sir I didn't understand case 3rd kindly someone explain.

what happen if there was no layer of SiO2 ...

Can u explain case 2 nd 3 again . It's very confusing nd it's not clear. Case 1 is very clear.

Nice explanation but please clear the board from time to time while explaining it is easy to understand. When writing case-2 and case-3 the diagram was not visible.