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Design Guide for Bootstrap Gate Driver Circuit with LTspice Simulation 

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7 сен 2024

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Комментарии : 7   
@majidhyderi-jimmy5588
@majidhyderi-jimmy5588 4 года назад
Can you send me the link of simulation file?
@prabhatkiran3226
@prabhatkiran3226 3 года назад
Thanks for the informative video. Can there be any disadvantages in selecting a too high value for Cbs? For example, if I use Cbs>1000*Cgs what will happen?
@Charged_EE
@Charged_EE 3 года назад
Disadvantages: 1000*Cgs capacitance will be costlier, It will also consume more board space if belong to same type (e.g. Ceramic) and lastly it will take longer to reach full voltage and hence transient performance will be slower.
@prabhatkiran3226
@prabhatkiran3226 3 года назад
@@Charged_EE Thanks for the reply. If you don't mind, I have another question to ask. In many examples, I have seen another low-value capacitor used in parallel to Cbs. Is this necessary? Or will the circuit work just fine if I use just one appropriate capacitor?
@Charged_EE
@Charged_EE 3 года назад
@@prabhatkiran3226 depends upon your layout...if your boot-cap is located far from gate driver pins then you may want to put some low value bypass cap on the pin-out of the gate driver.. this is done to compensate drop in trace inductance and smoothen the waveform..
@prabhatkiran3226
@prabhatkiran3226 3 года назад
@@Charged_EE Thanks man. You cleared my doubts.
@memmedshamurov1639
@memmedshamurov1639 Год назад
What about gate-source resistor around 10k?
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