Fun to see how Dave's presentation style and confidence has improved as well as everything to do with his own video production as he has made more and more videos and become so well known. Brilliant stuff.
I just asked about why would you limit the current to an OPAMP input on Reddit today, this video was suggested as part of the reasons ;) 11 years now hehe
Thanks, you totally saved me, tomorrow I have an exam in VLSI and this subject always comes up in exams... Thanks a million man, you have put up there the most comprehensive explanation I have come across...
I was going to use a PTC to limit the current to a motor driver, but when I started hearing about "latch up" I was worried that would happen if a control input was present while the voltage was being dropped (i.e. the PTC "tripped") but now I see it's as simple as adding a couple diodes.
Still a great video 14 years after it came out and it is not only young players who can "kamagatcha". I would like to see a practical followup on it where a circuit is exposed to latchup and an identical one is protected
Wow, Dave has been at it for a while, eh? I only encountered latch-up in my own project yesterday, while connecting a lead wire from the gate of a PNP Mosfet to an external frequency counting circuit. Sometimes the Mosfet would turn on permanently (when I moved the probe wire), despite the fact that the gate driver's collector was still oscillating ... and despite the fact the gate was protected by a zener. Mysterious. Well, now I know ... maybe all power MOS drivers need a clamp around the gates?
Very nice explanation, Thanks a lot. I think there should be an n-well sketched, if not , reasoning for the n-diffusion which is connected to the vdd can't be satisfactorily described/reasoned for being there. Thanks again for the knowledge, your effort for making this video.
Excellent description. Some moron at work designed a board to inject 5V signals into a 3.3V micro. I will send this to him to help him realise he is a clown and needs to fix it. The easiest is to put a 1R 2R volatge divider on the output.
You did not mention one other common source for latchup problems, namely incorrect power sequencing for a board/chip (which led to my first excursion into latchup problems), I assume due to making the video shorter? Still important to know IMO
Hi, Can you tell me why the SCR characteristics has negative resistance and how is it explained? I've have been searching for this explanation for a while. Thanks in advance.
@creativeengineer AVR's, and others I'm sure, artually have builtin clamp diodes, meaning it's actually pretty safe to connect an input of such a 3.3V device to a 5V signal. For a cool side effect of this, google "avr rfid"...
Would something like this cause an IC power rail to act like a resistor, I've had some cmos based chips that for some reason draw a lot of power but still somewhat function and a resistance is present on the power rails usually in the order of 40 odd ohms, my guess is the output mosfets latched up and "burned" in a resistance to the power rails
What you're describing is most likely high current draw due to a floating pin. Do a search on "cmos floating input" - e.g. electronics.stackexchange.com/questions/7179/is-it-really-a-bad-idea-to-leave-an-mcu-input-pin-floating
Interesting, I've seen similar in the past as well. I believe latchup is generally cleared by power cycling. It could still have been internally damaged due to the excessive current flowing through it, caused by either latchup or a floating pin. Or possibly more likely caused by ESD damage.
@arunkumar446 scr I-V charectaristics go linear(ohmic,increasing gm) and then take a negitive slope when latchup occurs and then I increases very drastically
Can you make a device that would give an electric shock, everytime it hears the word "Actually"? Then, redo this video, while wearing said device? I'd watch it....
