Thanks for your video, very informative, I do have a question: What's the disadvantage of 2D chaplet package? besides the bandwidth between the dies? Taking AMD's Ryzen CPU as an example, I believe they use 2D package, the Die to Die communication has to go through the wire in the substract, is there any significant disadvantage of this package method?
Disadvantages of 2D chiplet package - "Who will solve technical issue?" can be challenging if there are multiple suppliers for each die in chiplet with multiple dies. Test for chiplet can be another challenge. Disadvantages of 2D chiplet package for AMD Ryzen CPU - Sum of die area is larger than SoC with duplicated circuit at each die for die to die communication. Package size of chiplet with larger die area can be larger than SoC. These are some disadvantages but I don't think those are significant disadvantages because there are many benefits as well. Please check below link for your reference. www.gsaglobal.org/wp-content/uploads/2023/02/2022-IPIG-Heterogenous-Integration-Chiplets-White-Paper-Final-v4.pdf
Usually it uses microbump and silicon interposer. So it just needs normal heat from reflow process which is common for flipchip attach process. Please check my other video about 2.5D and you can see how microbump(ubump) looks like. [Eng Sub] 2.5D Package Technology: GPU+HBM, AMD, nVIDIA, TSMC ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-EuBRa3NWMPs.html
Appreciation for sharing the chiplet of heterogeneous integration. Could you please share some ideas on TSMC's advertising talk on the HotChips this year, e.g. SoIS (a fancy tech to beat conventional ABF substrate) and SoW (Tesla's Dojo system)? thank you.
![[Eng Sub] Chiplet](/img/logo.svg){kind=logo}
