Ep7:Trending questions on CMOS inverter | NOISE MARGIN | JOB or MTech admission interviews|

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Learn Verilog with Practice : www.whyrd.in/s... The most important question asked in a VLSI interviews
Ep:8: • Ep8:Trending questions...
Ep 1: • EP1:Trending questions...
Ep 2: • EP2:Trending questions...
Ep3: • Ep3:Trending questions...
Ep4: • Ep4:Trending questions...
Ep5: • Ep5:Trending questions...
Ep6: • Ep6:Trending questions...
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The VLSI interview preparation tutorial will help you to build a strong aptitude towards the most asked VLSI questions in the job/MTech admission interviews.
I will help to give the way I approach any problem and then explain it to the interviewer.
About myself: Hi, I am Rajdeep Mazumder, I did my MTech from IIT Delhi in Radiofrequency design and technology. Presently I am working as a hardware engineer with Intel. I am an engineering enthusiast and daily meditator and want to build hardcore engineering teaching as my profession.
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Disclaimer: All the views and information shared in this video are as of my best knowledge but please counter-verify all information again. Here I am representing myself only. All the Guest have their own responsibility for any view taken forward on this platform. I made all my effort to share only the information which is already publicly available. No confidential information is being shared.
#whyRD #VLSI #cmos

Опубликовано:

8 сен 2024

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Комментарии : 18

@rajkumarsah5416 Год назад

I got selected In Synopsys yesterday. And their favourite topic was CMOS inverter.. This Playlist came very handy just at the right time. Thanks ❤️

@whyRD Год назад

And thats thats make my effort worthy ,thanks a lot for this good news Rajkumar ❤️

@rajkumarsah5416 Год назад

@@whyRD Grateful 🙏 Keep doing the good work bhaiya.

@430kadajaganmohanachari9 Год назад

Super sir please continue making videos you are awesome

@savinaykumar1469 Год назад

Thank you for your great work and support

@harshmaniyadav9578 Год назад

good work......

@harshmaniyadav9578 Год назад

please make videos related to Analog design...…thanks

@faneeshbansal Год назад

6:37 ,but now if i input values between Vil and Vih , then what would be my output sir?

@manoj3197 Год назад

I guess based on equating the polarity of the noise signal with applied input signal the input is determined and results in corresponding output...

@faneeshbansal Год назад

@@manoj3197 yes as gain is very high in that region , so finding the output is very difficult as a minor noise in our input can change our output values

@faneeshbansal Год назад

But in the range 0 to Vil, that is noise margin low , all inputs value is considered to be low, so our output is high, in that region , our gain is = 0 , so whatever noise is coming , it is being killed by our inverter , So a good inverter is capable of killing the noise at its output to give us specific output

@manoj3197 Год назад

@@faneeshbansal yes So noise doesn't make any differences for the output when it's introduced in region 1 and 3 Any ideas on What would be practical conclusion if noise is introduced in region 2?

@faneeshbansal Год назад

@@manoj3197 yes the inverter is killing the noise as gain is 0 ( because the dvout/dvin) is zero, can't comment on section 2 because the output here is completely dependent on noise , a small noise can invert our output.

@DanishMalik-my6li Год назад

HI I was thinking of joining some vlsi training institutes like maven silicon and other like it. I want your views on this. Do you think this will be right move. Because for last many months I am seeing many people linkedin profile, many people have done training from these institute. Please suggest.

@whyRD Год назад

depend , let me summarise all my views in a video next