At 1:56 I don't understand how the P-MOS can be activated by the 1. If '1' is logic high (3.3V/Vcc), then the voltage of the gate relative to the source (Vgs) is simply 0, and the P-MOS is not conductive. To activate the P-MOS, Vgs needs to be negative -- that is, the gate voltage would need to be logic low (0V/GND) while the source voltage is 3.3V/Vcc, meaning Vgs = -3.3V. And again, at 2:21 , if there is 0V on the gate of the P-MOS, the P-MOS will activate due to the negative Vgs, which means both mosfets will activate and Vcc and GND will be 'shorted' by the connected drains. What am I missing?
1:03 The diagram has some mistake. The output Gate should not connect to both the PMOS and the NMOS. There should be 2 different gates connecting to different MOS. Otherwise, you could not get the desired control result.
Nice try and pictures but it would be much clearer for beginners not to use a PMOS transistor with Gate inverter. Instead, I would draw an external one.
