This is a world class stuff provided by the owner of this channel. I know there arent much views but may be in some time as the whole world is going towards internet, i see this lecture getting millions of views. Kudos
any day, when an industrial professional explains a topic, it is very easy to follow. Very good job Sir. Hope to see many more videos. Please keep posting.
12:07 Serical protocols: CAN - Controller Area Network Ethernet - Internet I2C - small devices SPI - Low speed peripherals RS232 - present in computer USB - phones, laptops, SATA - harddisk MIPI - Mobile parts - camera and display unit
Thank you. It's really helpful to watch this set of videos to understand that basics of Serdes concepts. Could you add the subtitle to those videos? Or auto subtitle would be helpful as well.
Beautiful video. Fantastic slides and presentation. Thanks a bunch. A small correction around 13:26? Memory bus is a parallel communication. This is correctly shown in the slide. But the audio accompanying it gives the feel as if memory bus is serial. Am I missing something here?
Hi Sir, It's pretty good info of serdes. as per the explanation the equilizers are required to boost the attenuation frequency, In that case why do we need equalizers at receiver end??
20:32 Here the design of equalizer is depending on channel. So at later stage of layout a Equalizer circuits needs tuning based on channel length? ( You mentioned channel will be few buses, In layout terms we can say high metal routing right . please correct me If I am wrong w.r.t this statement)
Hi sir, it was a very good overview of the high-speed serial link. Will you make more content in detail about this? If not, please tell some good references to study high-speed serial links in detail.
Hi Subhodh.. There are two more videos.. One speaks about CTLE and another serdes layout.. Please go thru.. Also go thru all comments... There are references..
@@analoglayoutdesign2342 Thank you very much for replying. I have watched the CTLE video also. Actually, I have just started working in this field and observed that not much content is available for beginners on the internet regarding this field. I have subscribed to your channel in case you make more detailed content. Thanks again.
at 4:00, I am confused as in 2nd point it is mentioned parallel has higher data rate, while last point tells it has lower data rate. As last point is in MBPS, which is data rate. Should it be in terms of clk speed ? like MHz and GHz. Data rate of parallel will be (no of data bit)*(spd of parallel in Hz)/(speed of serial in Hz) faster than serial. 2nd point and Last point together makes sense if units are in Hz.
very good lectures.....but sir one suggestion for you....please use good quality mic....your voice has air disturbance. may be you are talking very near to mic.
LPDDR , HBM and DDR are parallel interface. In fact most memory interfaces other than HMC are parallel. Also there is no SERDES phy in LPDDR. Pls make that correction in your video.
Hi Sir i have a dout like why the channel will send week signal to rx , as it's giving strong signal , is it due to capacitence or any other , please clarify this one by anyone
The main problem I see with parallel interfaces is cross talk. Could you please refer me to some crosstalk cancellation circuits? Other issues are data at receiver come at different times.
if all of the protocols use SERDES, why do we have different SERDES? ans: 13:18 PHY means physical layer Vlsi engineers work on Physical layer Every protocol has physical layer with different speeds and requirements etc.,
I have worked many years with SERDES and I find your explanations very poor. The beginning is missing many explanations: the clocking & synchronization. The channel model is not good: an RC is ok for low speed but for SERDES they use transmission lines which the attenuation vary inversely with the square root of frequency. Equalizer need more explanations. SERDES clock recovery, synchronization and word alinging infos are missing. Table that show PCIe is a parallel bus is incorrect! Although PCIe appear as a parallel bus they use many serial lines in parallel which must be sorted (another missing info).
Dear Andre, you are commenting this after many years of work. If you were in your first year, may be, you would have appreciated it... This is a high level basic introduction... This channel is intended for beginners and engineers with lesser exp. I personally don't believe to introduce a complex system ...rather introduce a simple system and add complexities later...for ex RC initially and later tx line...for such reasons only they teach 8085 or 8086 processor and not intel core i7... :)
Dear Andre, you better to make a video for giving proper insight and explaination, instead of commenting here. So that the others will also get benefitted by your experience.
@@analoglayoutdesign2342 Hi Sir, please upload more videos on digital and analog as this is very very useful. I am seeing only limited videos in this channel.
