SERDES LAYOUT (WIRE / INTERCONNECT PARASITICS) 

Nice lecture! Looking forward to one on DFE and TX Equalization techniques.

Good contet in lecture sir and we'll explained👍. If possible please provide more videos on high speed serial links.

Thank u sir for the wonderful content!!!

Thickness is dependent on the metal stack options for that particular node..as we go to lower geometry process ..thickness also has to decrease..

Great lecture with clear examples. Can you share the part2 of this topic pls? Thanks.

You are awesome!! You make great content to learn from. Easy concepts and examples. Thanks a lot!

Thank you Sir for the lecture! It is very helpful. Just wondering if there is a plan to teach the part2 in the outline (inverter input and output parasitic capacitance, and propagation delay)

Thank you for good lecture sir! I have one question on parasitic resistance. As you know resistance increases with frequency due to skindepth. For SERDES, operates are in GHz range, don't you think per sqaure sheet resistance is under estimate of parasitic resistance ? Would this be significantly higher ?

You have explained about parasitics calculations but can you please explain me how it effects that signal? and how that leads to circuit degradation?

Hi Jay, May I know which company you work for? Thanks, Sai.

Hi thanks to your videos...can you please make videos on EM/IR and how to calculate it, antenna, lod, sti topics.

Hi Please provide video on ring oscillator waiting for current mirror part2 andsub 1V BGR

Also waiting for your sub 1V BGR video :)

Please make a video on ADC PROJECT ????? ND MORE VIDEOS ON FINFET ????

Hi sir When you'll post matching techniques and op amp operation videos

can you give me the classification about 2nd order effect and short channel effect

scripting languages videos for vlsi