Very cool. A few months back out of boredom I built a full adder from descrete transistors. Had a lot of fun optimising the design to find the minimum number of transistors needed. Also looking forward to seeing this unit progress. I already figured out the add, subtract and multiply modules, but the division section is melting my mind. Found a design that annoyingly mostly works, except it has some random combinations of inputs produce completely erroneous results 🤨
Thanks! 🙂 Can't wait to integrate this into the CPU. Thinking about having separate multiplier and divider units later on that work iteratively across multiple cycles. Building an adder up from discrete transistors sounds like a very nice project, love it! 🥳
It seems RU-vid has eaten my last comment 🤔 Anyways, my point was that at the current clock speeds it should be possible to build circuits that could do multiplication and division in a single clock cycle, but I agree that as they are likely to have significant propagation delays it would probably be a good idea to pad them out to avoid issues. Oh, and this is the circuit I found for division https [://] userpages [.] umbc [.] edu [/] ~squire [/] cs411_l10 [.] html Seems to work fine so long as you treat it as a 4/4 bit divider, not the 7/4 bit that it describes
Wonderful video! I really enjoyed the thorough walk through of the boolean algebra! It helped me understand the connection between circuit design and complexity theory (dual of 3-SAT). Keep it up! I always look forward to these videos! :)
In a real world situation it is often better to use more gates and reduce logic layers to reduce propagation delay, this is where the tools you were discussing really become essential. This was a nice explanation but I thought you would use Karnaugh maps rather than going the boolean algebra route. Still I suppose algebraic simplification is easier for many to understand exactly what is going on.
Excellent point about favoring speed over minimum number of terms! 👍 A common strategy among those tools is to do an initial minimization to the most compact boolean expression, then map to the logic gates available and start optimizing/replicating to improce timing. Love those tools, always feel like magic. I was considering Karnaugh maps. They would work quite well here, but going beyond 4 or 5 inputs with them is very difficult. Boolean algebra rewriting is a bit more general in that it'll just keep working, but has its own downsides and scaling issues. If I recall correctly, minimization algorithms like Espresso use a form of higher-dimensional Karnaugh maps and boolean rewriting in combination.
The fact that one can reduce a truth table into DNF is the basis of the PLA chip design. They are structured in the same way, AND gates generating terms that are then ORed for the outputs.
For tables more complex(with a lot of inputs) than a truth table, it is simple to use karnaugh maps, for a simple table a truth table is enough. AB\C 0 1 00 0 1 01 1 0 =>C'A'B + C'AB' + A"B"C + ABC = C(A'B'+BA) + C'(A'B+AB') = C(A'^B')+C'(A^B) 11 0 1 10 1 0 For cary: AB\C 0 1 00 0 0 01 0 1 =>AB + AC + BC 11 1 1 10 0 1 Another way is to simplify the truth table, select the rows where outputs are 1 and add them for example XOR gate: A B O 0 0 0 0 1 1 1 0 1 1 1 0 So what we notice is A = 0 and B = 1 outputs 1 or A = 1 and B = 0 outputs 1, we can translate the function above into: O = A'B+AB', this can be also noted O = (~A)&B | A&(~B) If the output function is too big, it can be simplified using simple math, example OR Gate. A B O 0 0 0 0 1 1 1 0 1 1 1 1 O = A'B+AB'+AB = A(B+B') + A'B = A + A'B =A+B Rules: A+A' = 1 A+A'B = A+B A' = ~A AB = A&B A+B = A|B
Karnaugh maps are definitely a great approach here 👍! They do struggle with more inputs though: if you have more than 4 or 5, it becomes hard to draw the grids and find the covering rectangles, because you run out of dimensions on the 2D sheet of paper that you're writing on. And with Karnaugh maps you'll still need a separate step to rewrite some of the AND/OR ops into XOR ops. That's why I went with boolean equation rewriting from the beginning: theoretically works with any number of imputs, XOR comes more naturally, and you could just stubbornly try rewrites without understanding what they do and you'll get a half-decent result. 😇
Just be thankful he only showed ripple carry adders. Explaining fast carry adders (like the 283 IC mentioned) would almost certainly double the video length 😅
@@mekafinchi not much point in explaining a circuit that's wholly impractical to build though is it? Also, it's the overall function that's important, as we're not going to be using discreet logic gates in the final design. I'd also add most people would likely agree that understanding how to solve a problem is more useful than just being given the answer and so appreciated the explanation of different approaches. Finally, I'm sure there's plenty of other videos that go into detail about the design of fast carry lookahead adders if that's all you're interested in.
