How to Access Registers - Superscalar 8-Bit CPU #17

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A processor's register file feeds data to the executing instructions and stores their results. In this video, we combine the register file and instruction fetch unit from previous episodes and take a closer look at how instructions can read and write registers, and deal with constant values that are part of the instruction stream. In doing so we extend the instruction encoding of our CPU, add "load-immediate" and "move" instructions, and introduce a new flavor of "jump" that works with registers.
This video series explores the concepts and techniques that make modern computer processors so incredibly fast and powerful. I build my very own 8-bit processor from individual logic gates and gradually evolve it to become a superscalar out-of-order machine. Along the way, we take a deep dive into contemporary computer architecture in a hands-on fashion and rediscover some of the foundations of modern computing.
Previous Video: • How a Register File Wo...
Series Playlist: • Build a Superscalar CPU
- Register File: en.wikipedia.org/wiki/Registe...
- Three-Address Code: en.wikipedia.org/wiki/Three-a...
- RISC: en.wikipedia.org/wiki/Reduced...
- CISC: en.wikipedia.org/wiki/Complex...
Chips:
- 74HC541: www.ti.com/lit/ds/symlink/sn7...
- 74HC139: www.ti.com/lit/ds/symlink/sn7...
- 74HC04: www.ti.com/lit/ds/symlink/sn7...
00:00 - Intro
01:20 - Multiplexing Immediates/Registers
05:34 - Immediate Buffer
13:29 - Testing
17:41 - Updated Instruction Encoding
21:55 - Connect RegFile and InstFetch
27:46 - Adding New Instructions
34:11 - Writing a New Program
41:30 - Testing
48:25 - Recap
51:20 - Outro
#homebrew #8bit #breadboard #superscalar #computer

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Опубликовано:

17 июл 2024

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Комментарии : 24

@JaenEngineering Год назад

Comment to say keep up the amazing work. Looking forward to the next episode in this build.

@catgirlQueer Год назад

very cool! can't wait to see this go scalar and beyond

@mrengstad Год назад

Nice job! One thing though, your NOP is now encoded the same way as MOV R0, R0, so NOP is now a pseudo-instruction (that burns power).

@fabianschuiki Год назад

True, although there's a subtle difference: registers r0 and r1 are encoded with addresses 1 and 2 respectively. Address 0 is unconnected/unused. The nop instruction is encoded as `mv unused, unused` (reg addresses 0), so the processor is neither reading nor writing any registers. I don't think there is any nop being executed in the video, so this behaviour isn't totally obvious.

@davidrosset4457 3 месяца назад

Interesting, I followed your GPR Easy EDA schematics exactly to hook up the 74HC377 to the LED's. However, I had to switch bits Q5 & Q4, and also Q0 and Q1 to make it work... But the schematic seems correct, I wonder why this is

@fabianschuiki 3 месяца назад

Huh, that is strange. I did flip some of the bit order around, just to make routing easier. But that shouldn't affect the result, as long as you get the D and Q pairs right. 🙂

@yashindane2844 3 месяца назад

Hi Fabian, what's that long ribbon cable exactly called, u used at 23:36 ? Its different from rest of the cables.

@fabianschuiki 3 месяца назад

It's also a ribbon cable, but just one that doesn't have all the colors. This one in fact was home-made: you can get entire spools of those cables, and crimping kits to attach your own pin headers. They are pretty cheap on Amazon or AliExpress 🙂

@christophfriedrich5092 Год назад

24:39 If WA and RA1 are the same, why not ditch one chip and use the same output from the demultiplexer for WA and RA1? Then you could use the other demultiplexer part on the chip for RA2.

@fabianschuiki Год назад

Yes you are totally right, that would have saved me a chip! In the following episode on absolute jumps, I'm combining the RE3 signals with the RE2 signals to save a chip. Could have done the same for WE and RE1. Once we move to register renaming, we are going to need four separate decoder chips, because the physical registers no longer correspond 1:1 to the assembly/architectural registers.

@christophfriedrich5092 Год назад

@@fabianschuiki Makes sense ^^ Thx for the fast answer.

@reinoud6377 9 месяцев назад

Is there a specificaties reason to go for 2 operants opcodes instead of 3?

@fabianschuiki 9 месяцев назад

It uses fewer bits in the instructiom to encode. For example, if you have 16 regs, you need 4 bits per reg operand. That's 12 bits just for operands if your instructions encode three operands. I want to have 16 bit instructions. Giving up 12 bits would mean only 4 bits are left to encode the actual operation. That's only 16 instructions, barely enough for an ALU. Two operands means only 8 bits are used for operands, and I get the other 8 bits to encode the operation. 256 instructions 🙂

@user-mr3qc4mg5v 4 месяца назад

Electronics is insane

@fabianschuiki 4 месяца назад

And a lot of fun 😃

@JaenEngineering Год назад

I know I already commented, but I was curious to know if you have a use for that last unused bit? If you have, then just ignore the next bit of my comment but if not, how about using it for a "Jump IF" command, so the PC jumps only if some other condition is met?

@fabianschuiki Год назад

Yeah that is a pretty good idea! We'll also somehow have to indicate to the future arithmetic unit whether it should write to the register file. At some point we'll need an instruction decoding mechanism that allows us to assign more than one functionality to each instruction bit. Until then I think we can make some good use of the existing spare bits in the instructions 😊

@JaenEngineering Год назад

I worked out that it could be done with a single chip. By placing another 153 muxer to intercept the mode select lines between the program memory and program counter the muxer selects between either forcing a step, or passing through whatever jump instruction the program memory outputs depending on muxer select pins. One is the "jump if" bit, and the other a flag. If I've got my logic correct it should work without breaking any current functions. You use the spare bit as the 'jump if' instruction, and the destination register to select which flag you want to check. You can still use the upper byte to either provide an immediate value or access a register. Speaking of program counter modes, there's still a "spare" mode after the step/rel/abs modes. Not sure what it could be used for (I was thinking a return address maybe?), but it would need a new PCB as I think selecting that mode currently resets the program counter. [edited to add; I originally thought of using this spare mode as the conditional jump but it requires two instructions to execute the jump. I also thought it would also require remaking the program counter board however I've realised it can probably be done with the board as is] As for the ALU, I've not really thought that far ahead! Lol! I was actually trying to figure out a flags register that would allow you to set individual bits then read them back. Some would be immediate (ALU overflow, Zero, Negative, busy, etc) and some that can be set (carry in/out, full).

@CeDoMain Год назад

While the ping pong at the end is running i see, that the reg2 is randomly selected between instructions. why is that?

@fabianschuiki Год назад

This is related to how we are extracting 16 bits in one cycle from an 8 bit memory from back in episode 13: ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-LvwrQ-nwZg0.html. During the first half of the clock cycle, while the clock is high, the upper byte of the instruction is visible on the upper and the lower 8 bits of the instruction. It's only during the second half of the cycle, when the clock is low, that you see the full instruction. That's why there is some random selection happening for the first half of the clock, between instructions. At a later stage we'll want to feed the instruction bits through a register for pipelining and stalling, which will get rid of these glitches again.

@CeDoMain Год назад

Ok, so because one latch is transparent for a short time of the clock cycle? It lets through the other byte of the instruction?

@fabianschuiki Год назад

Exactly! And when the clock goes low, the latch holds on to that byte (which is why one of the instruction bytes stays fixed -- that's the one from the latch) while the other byte updates to what the memory is producing (that's the one directly attached to the memory).

@donwald3436 Год назад

instruction decoder.......

@fabianschuiki Год назад

Coming up soon! It's still interesting though to see how far you can get withou an instruction decoder. Also helps keep the instruction set streamlined and organized.