Thanks so much Robert for inviting me on and the wonderful chat we had! It was so nice to collaborate with someone who has the same passion for helping the EE community, albeit in different disciplines.
Hi @FPGAsforBeginners, thanks for sharing your experience. One question I had in mind. Why using raw sockets rather then udp ones ? Is it because of some checksum issues, or unexpected data in packet ?
I'm following you both but I wanted to say that you have a great chemistry for teaching digital electronics. I hope you will collaborate again in the future!
The moment you said that no IP blocks would be used, you got my full attention. Thank you so much for this informative and fun video. I have an Ultra96 V2 and some RMII Ethernet modules. Looks like I'll have to follow along.
Awesome. this You tube channel cs and electronics students must follow. the information we can grab from here is more than a text book. also he upload videos like this for free. you are awesome Robert.
for those who wants to repeat this wonderful course but their board do not have so many LEDs and buttons (I use qmtech kits very often for my tests), I propose to use the virtual input/output module from Xilinx IP list. From my side I might have some questions regarding SDIO PHY configuration interface. Since it was not used at all, I suspect it was used as it configures itselves in the negotiation sequence when the PHY was connected to the switch? In such case I can use any PHY ASIC? Even 1G if ASIC sustains the RMII communication option? How about if to connect directly to PC, and the PHY ASIC is able to detect the crossover cable, the configuration over SDIO bus still can be avoided or not?
Hi, I'm working with a zynq board implementing udp using the built in arm. I'm looking for an example implementing the software for the connection. My remote host is connected via a python socket, and I'm trying to correct for dropped packets. 🤔
IP does not show after adding repository... Not sure what is the issue. I can successfully add IP repo. But when click on + in the design, it will not list those. I tested in both 2023, 2024 version. Changed the board but still not working. Any help appriciated.
based on the example you can easily transport the data over local network to a standard PC/server and then run there an application to extract the data and do anything you need.
Usually for TCP/IP you would implement it purely using software on a softcore processor instead like a Microblaze or a hardcore processor like Zynq/Zynq US Processing System connected to an AXI crossbar.
from the design of implementation in this video, it may suspect that was used between 5K and 10K resources, but it can be less as well. If your tango has 20K no worry about
@@cccmmm1234 you can send the packets on something like spi and then to ther microcontroller do not solder your cat 5 or cat 6 cable to tang nano it will not be eletricalky correct