How To Do Ethernet in FPGA - Easy Tutorial 

Thanks so much Robert for inviting me on and the wonderful chat we had! It was so nice to collaborate with someone who has the same passion for helping the EE community, albeit in different disciplines.

So cool that you are having Stacey on! She has great enthusiasm and is a good teacher!

the tutorial the FPGA student community deserves!

Thank you Robert for discovering talented people on RU-vid and introducing them to beginners and engineers.

Stacey is the best ever, very important video as usual

I was litterally trying to do a project with Ethernet and a Spartan6, this was so helpful to understand the concepts

Yay Stacey! Her gentle enthusiasm and clear competence is wonderful

I'm following you both but I wanted to say that you have a great chemistry for teaching digital electronics. I hope you will collaborate again in the future!

That was great! I've never touched FPGAs before, but this video makes them feel approachable.

Awesome video & collaboration! Great job Robert!

A dream come true please make more videos together. Wonderful (-;

This is why we've subscribed! Amazing!

The moment you said that no IP blocks would be used, you got my full attention. Thank you so much for this informative and fun video. I have an Ultra96 V2 and some RMII Ethernet modules. Looks like I'll have to follow along.

I love this so much. Very informative

Awesome. this You tube channel cs and electronics students must follow. the information we can grab from here is more than a text book. also he upload videos like this for free. you are awesome Robert.

Simply excellent ! Thanks

thank you for this educative video

Awesome collaboration. Both if you work well with other people.

Nice. Please make a video on designing custom IP modules in Xilinx Vivado.

Good tutorial

for those who wants to repeat this wonderful course but their board do not have so many LEDs and buttons (I use qmtech kits very often for my tests), I propose to use the virtual input/output module from Xilinx IP list. From my side I might have some questions regarding SDIO PHY configuration interface. Since it was not used at all, I suspect it was used as it configures itselves in the negotiation sequence when the PHY was connected to the switch? In such case I can use any PHY ASIC? Even 1G if ASIC sustains the RMII communication option? How about if to connect directly to PC, and the PHY ASIC is able to detect the crossover cable, the configuration over SDIO bus still can be avoided or not?

Good.

Great job!

🤩🤩

Most Excellent! I think FPGA's are a little bit neglected. Maybe because they're so complicated.

Hi, I'm working with a zynq board implementing udp using the built in arm. I'm looking for an example implementing the software for the connection. My remote host is connected via a python socket, and I'm trying to correct for dropped packets. 🤔

IP does not show after adding repository... Not sure what is the issue. I can successfully add IP repo. But when click on + in the design, it will not list those. I tested in both 2023, 2024 version. Changed the board but still not working. Any help appriciated.

OK, so this is the hardware part of Ethernet, but there still has to be some kind of software for a TCPIP stack to transport the data?

Is there anychange that this IP works for AES-ZUB-1CG-DK-G ?

Can I use this module with 2018.2 because I got some warnings problems.

how to make it work for Arty A7 100t ? It does not have CPU_RESET pin

how many luts does this project consume. how easy will it be to port to tang nano fpga

Rodriguez Dorothy Lee Daniel Johnson Jason