This video contains out-of-date information about how AMD CPUs are put together these days. They have an IO die that has the interconnects between the CPU dies, and the IO die is also how the CPU dies reach the rest of the system.
Not just that, but the IO die is using an older, larger lithographic process as it doesn't really gain any benefit from moving smaller, which is one of the reasons he gave for Intel's move to a tile-based design.
The 20A is likely 20 Angstroms, which is 2 nanometers. I assume that this is because they need granularity for future nodes - they can call the next next next generation 15 A and so on.
i can't wait for the reviews showing if their efficiency first approach is able to also increase performance in some way. I feel like ryzen has been dominant for some while now and maybe this will shake things up a bit.
I sure hope the scheduling works properly in different applications. Or I'll have to pin processes to cores with some sort of utility or taskmanager or something
It already does. The different cores only had scheduling issues for like the launch month back in 2021 of 12th gen. 2 years later and its completely flawless. Having the e-cores enabled benefits most games anyways, even though they arent the high performance cores.
@@__aceofspades Besides Cyberpunk 2077 and BF2042, no other game benefits from e-cores. The scheduling works fine now, but we talking about 14th gen here, where a third set of cores are a thing and the weakest cores are prioritized. Hopefully that prioritization isn't a thing with games.
3:25 This is a bit misleading. The actual length given haven‘t meant anything in particular for a good while now (it used to be the lithographic limit, the feature size, now it is just named so scaling roughly behaves as it did back when we actually directly scaled via feature size alone). Intels renaming was for a good reason, in terms of transistor density their Intel 7 process is somewhere around TSMC N7 and N7+. So it is actually directly comparable, their 10nm process just used to be way better than anything else, so they changed their marketing to be in-line with TSMC again.
I am not an expert but it was my understanding that it is not possible to compare transistor sizes between samsung, tsmc, intel etc as they each use different ways of measuring so intel wasnt necessarily behind but that they have been stuck on their 10nm for a long time (by process node time scales)
You can't compare transistor gate size (which is what the NM number used to come from), and there are other factors that matter, but you can compare transistor density. Doing so puts Intel 10nm (now called Intel 7) slightly behind TSMC 7nm, which debuted in 2019. Even if Intel hurries and finishes Intel 4 soon, it will probably be on par with TSMC 5nm, which will still put them a full node behind.
@@capsulate8642 given that it is interesting to see how close in performance intel is able to get compared to amd. I assume that it shows the importance of the aspects of chip design aside from transistor density. My I9 does get very hot though even with a 420mm rad, probably something to do with the sustained 310W
@@MrTeddy12397Anastasi in Tech has a video explaining that the "nm" is the theoretical transistor size of an equivalent planar transistor. Since current transistors use different techniques such as finfet and gate-all-around, they cannot be compared in any meaningful way
@@MrTeddy12397 I believe that is because of some 3d stuff they are doing that makes them equivalent to 2nm which is what makes it hard to compare cause they all have different ways of working that out
What do you mean the structure is similar? Are you comparing the stylized "die shots" (they are not very accurate) that Intel and Apple show? Or do you mean the P- and E-cores? (Intel started doing this with Alder Lake which came out in 2021 and most ARM based chips did this already) The most important distinction is that Intel creates multiple dies and combines the functionality of each die to create an SoC (System on a chip) (using their packaging technology Foveros). Apple creates a monolithic die (fabbed at TSMC). Apple packages the M1, M2 such that RAM and the SoC is on the same package where as Intel does not do that (although they did show a test chip where there was on package memory (it's not exactly a unique concept), however, I don't think that is gonna be a SKU for their Meteor Lake lineup). There wasn't really a reason to mention Apple when the primary commentary was about chiplets / tiles.
Exciting stuff up ahead for Intel! While I'm glad the Ryzen series stepped up and brought some real competition to the CPU space. Great video as always!
Cool to see it's a mix of different types of lithography processes for the dies. It's kinda like Zen 3 with the I/O die being on 12nm while the CPU die is on a 7nm node. AMD does this as well for the RX 7000 series where the cache is on a older node because SRAM transistor scaling basically flatlined in performance. Interesting to note is that Intel wanted to do GPU tiles for Arc, but went with a monolithic design in the end. That would have been way harder to do than separating cache and graphics die (MCD, GCD) like AMD has done. There are massive advantages and I'm very excited to see the chiplet/multi die future!
Maybe I don't know enough about tiling but it seems the exact same as chiplets (i.e. multiple dies connected together) and suffer from the same disadvantages?
@@strawbaria The hope here is that beacuse each chiplet does different things (ie graphics, processing, io etc) there wouldn't be as much crosstalk and latency. only time will tell though.
@@strawbaria intel's version should have less latency but increased complexity and cost. but AMD has had several generations to improve the infinity fabric and they are also introducing the "Zen4C/5C" chiplets (their version of E cores). Zen 5 seems to be heavily reworking the cache system to reduce dependency on the infinity fabric and massively increase IPC (20 to 30% IPC increase).
@@lightward9487 lol i wonder :D right now im rocking a 5600x so I'll stick with AMD until i can't upgrade on am4 then ill have to find who has the best price to performance
I dunno if they can push the power savings into high clockspeeds and the tiles make it cheap to make we may have a pretty good jump in perfomance to price again
Meteor Lake is revolutionary changes for Intel, the biggest changes in a decade. Tiles (chiplets), new more efficient Intel 4 node, brand new CPU and IGP architectures (AV1 encoding!), 133% the GPU cores of last gen, focus on power efficiency, NPU (AI cores). This is basically the best of Apple and AMD combined, with even more.
@@MrVladko0 Nope, latest leaks just suggested that it was around 30% IPC and clocks about the same. Prior leaks indicated that it was around 20% IPC and a 5-10% clock increase.
The intels sect is still huge in eastern EU. People still sticking up to blue camp despite insane power draw and huge latency issues caused by tiny cores.
Especially in the mobile segment not enough manufacturers offered AMD cpus and there they were really way better if it comes to energy consumption. On tower PCs it does not matter too much, because most games are bottlenecked by the gpu or you already get 144+ fps.
So while Amd lower cost by designing 1 chiplet for both pc and server with different i/o die, intel is more flexible by designing many modular tiles that can be mix and match?
Sort of, though it means they will have to create multiple monolithic "SoC" dies for all sorts of applications. I guess they evaluated it and decided to not go with separate chiplets for compute, but some sort of chiplet design is necessary as the monolithic CPU and GPU dies are getting to a point where you wouldn't get many of them working from a wafer. nVidia also needs to switch to chiplets someday. Or not I guess, since they don't mind selling their GPUs for insane markups. If 5090 is really 50% larger, the price of that card will be in the thousandS, as long as the size isn't many chiplets combined of course.
AMD still had to design a separate dies for laptop. I beleave Ryzen 7000 laptops have like 4-5 different dies now with monolithic 4 core Zen 2, 8 core Zen3, Zen3+, Zen 4, and chiplet based 16core Zen 4 (which is the desktop die) all under Ryzen 7000 naming.
Hah, be happy that it's not the 1990s! Back then, you'd buy a new PC, and 2 months later it would already have been superseded by a newer, better, much faster generation of computers.
@@antred11 You're right! My father always tell me back in his days, building a "futureproof" PC was (and still) a bad idea. Just build a mid-range PC and upgrade it by time, no need to build high-end PCs for usual activities.
Meteor Lake is mobile, desktop gets Raptor Lake+ this year (10% improvement), later next year is when all these improvements come to desktop, so youre fine.
@unsubtract I agree that 20A probably means angstrom, but you are right it is confusing that it usually means Amperes. They should have used Å as it is the standard symbol for angstrom.
AFAIK AMD's CPUs didn't technically use chiplets until Zen 2. This is because Zen EPYC and Zen/Zen+ Threadripper CPUs were made out of chips which were effectively standalone CPUs while with Zen 2 AMD split the cores from the I/O and since then their server, desktop and HEDT CPUs are all built using two different type of chips. Regarding LP cores, It's going to be interesting if we see any performance regressions as a result of work going to the LP and E cores before it reaches the P cores. I think gaming might be especially affected.
@@talibong9518 It didn't. Zen/Zen+ Ryzen CPUs did separate their cores into two Core Complexes (commonly referred to as CCXes) however it was still all one chip. If we were to count that as a "chiplet design" then Intel CPUs with P and E cores would also count as a "chiplet design" since in that case you also have separate groups of cores within the same chip. Edit: to be clear Zen EPYC and Zen/Zen+ Threadripper CPUs used the same 8 core dies as desktop Ryzen CPUs which means that they also had 2 CCXes within each die.
Slight correction on the firsr point of the video. Foveros (or 3d stacked technology) and tiled approach (or procssor desegregation) are quite different. Foveros refers to how the tiles connected together while desegregation is the separation of manufacturing of the processor to reduce complexity. 14th is the first client product to be using the tiled based approach while previously server products like sapphire rapid has been using them. Foveros on the other hand is a new packaging technology where the tiles are being stacked on top on of each other, thus getting better power consumption and latency than AMD's approach as mentioned in the video
Which is funny cause the distance apart isn’t even 7nm, it’s 32 nm If it was actually named after the physical distance, we’d still be on 32 nm Which is nuts
3NM to 20A means they're going from 30 nanometers (30 Angstroms) to 20 Angstroms. 1NM = 10A. As you pointed out, these sizes don't actually mean much of anything anymore, as they definitely aren't measuring the physical dimensions of their transistors now. Intel reasons the latency induced by the SoC scheduler will be no worse than AMD's latency from their massive IO die to the chiplets over their infinity fabric. They're making up for their uncompetative power consumption issues on a larger node by using these E cores for most smaller processes on a system (OS management and simple application computations).
I went with AMD Cpu just because of efficiency. I think its nice to see intel actually try instead of overclocking the shit out of their processors. tho that forced lp e core on soc might cause latency and a lot lower single core performance. I'd say if these new processors can beat apples arm chips, it would be great
I'm a chief of information technology from Finland and have seen computers evolve my whole life. The scale of modern computational capacity rivals the vastness of outer space. It's getting bigger at an increasing rate. Mind boggling, and we've barely scratched the creative surface of what to do with it all.
I wonder when Intel is gonna make a gamer CPU that has RGB and fire decals on it or something. Or maybe make it case hardened with random patterns. blue gem i10 gamer edition will go insane with the overpay.
It depends what you mean. If you mean that the iGPUs get the capability to run games with raytracing and frame generation then maybe, but it will take some years to get the performance where additional tensor cores are really making sense on these small gpus eventhough they try to integrate it earlier. If you mean that AI is integrated in the cpu with ASICs and Software making use out of it, then they already do that, but as a user you won't notice, because it is more likely happening under the hood.
CPUs have gotten many gamechanging features over the years. You just don't really notice them, because you do not see them. For example ddr5, more cores, pcie 5, usb 4, 3d Vcache. The cores also constantly improve with new instruction sets, security and power efficiency. I know this is not really exciting if you are only playing games but when you need the performance and connectivity then these thing are gamechanging.
@@killersberg1 I mean you are right, but these features are not new. 3d V-Cache also only allows more Cache memory. Sure these features increase the performance of the CPU, but they do not enable new features.
@@Tri-Technology What is RT? It is a "new" feature but in actuality it is something that has been done for many years but now in realtime. Before we would just approximate lighting which was good enough 90% and RT doesn't really look impressively amazing when compared to good approximated lighting. I do not consider RT a gamechaning feature. The hype mostly stems from marketing imo. I think CPUs improved more relative to GPUs in the last five years, although they have been behind before due to intel so maybe that cancels out.
amd dont really use chiplets anymore, they only rely on them for the bigger cpus like the 12 and 16 core models, the 8 cores just have one chiplet with 8 cores
On process node naming, the "nm" hasn't reflected any physical feature for a very long time and today is in essence a pure marketing number. Intel's problem is the scale they chose was out of step with TSMC and Samsung, which is what they're correcting since Intel 7 and will be using going ahead. While Intel 7 might be previously known as Intel 10nm, it is comparable to TSMC N7.
Intel’s naming isn’t a mistake, it’s a correction for the previous naming scheme, intel’s 14nm node has always been similar in actual transistor size to TSMC’s 10nm node, so they basically corrected the naming scheme to match TSMC’s marketing, plus TSMC isn’t really innocent themself for naming one of their 5nm nodes as “N4”.
I dont really care whether they're really faster than last gen or not, all I care about is that we get at least the same performance from last gen but with half the power draw. I never thought Intel would manage to do this since they we're always laser focused on performance at any cost so I'm glad they managed to prove me wrong.
I hope that they will also be compatible with the Z690 motherboards like the 13 gen of intel cpu's are. Then it would be an easy upgrade for me again for the next generation
@@soundspark Well i have been using a 9th gen I7 until a couple of months when i upgrade to 13th gen I9. Im sure that i can use that CPU for many years until i need another upgrade for it.
20A could refer to being 20 angstrom (Å) which means 2nm. Maybe it sounds cooler that way, I don't know. Naming schemes aside, at that scale, if what they claim is actually true and it is actually a 2nm architecture, it will be a very impressive technological achievement indeed, because this means that they found a reliable way to overcome the quantum effect limitations that are rather prominent at this scale. To put it in perspective, that means that the gate electrode of the FET is only 20 ATOMS WIDE(!) (give or take). I can't possibly give an explanation as to how that could happen (as it must be a cooperate secret), but very cool nonetheless.
I think MCM is just a stop gap before a fully integrated single die solution. MCM chips rely on high-speed interconnects to communicate between the dies and the substrate. These interconnects may be susceptible to mechanical stress, thermal expansion, electromigration, and other factors that can cause them to break or degrade over time. This may affect the functionality and performance of the MCM chip. I will not be rushing to buy them.
Amd should probably do something like this, as the infinity fabric is already quite a bottleneck, they could combine tiling and vertical stacking for super dense processors
And also add 1 or 2 extra small CPU cores in the I/O die so the main compute unit can be completely power off in light load (browsing, watching videos, doing simple office task), further lowering the idle power consumption
20A = 20Å (Ångström) = 20 × 10⁻¹⁰ m = 2 × 10⁻⁹ m = 2nm...? I mean yeah smart play to change units but I'd've expected _after_ slipping below one nanometre (if this is even possible with our current physics/engineering knowledge)
@@lharsay sounds about right, I mean Philip mentioned in the video that 20A had an abstract meaning because they can't predict what they'll be manufacturing
Depends what you have. How much can you afford? Would the money do more good if spent on something else? Do you want to make a rational judgement and follow sound economics, or do you want something fresh to make you feel good about yourself? This kind of judgement in a commercial setting would perhaps be a feasibility study or a procurement plan. There will always be better products down the road if you can wait. And new stuff depreciates quickly. If you are mean, you might choose older or second hand kit. But, you only live once.
which generation will have the biggest "jump" in efficiency/performance/cost? Is it dumb to get 14th gen when you can wait for 15th gen. Or will 15th gen not be as exciting as the jump from 13th to 14th
Hey, is it possible to make the thing were it gives the task to the low performance one then moves it up if needed a toggle? Can it be turned on and off, for gaming for example, or is this a hardware design thingie? Im not very savvy, sorry for any mistakes
2:19 What does it mean that the work can't be done on the most efficient part of the processor? Does this work contain instructions that aren't implemented in that part of the processor or what?
Please turn the music down for future videos, it is way too loud and is really distracting. I need to listen to certain parts multiple times in order to understand what you said.
@@2kliksphilip 15th gen is going to be Arrow Lake on the 20A proccess node with backside power delivery, but we don't know details from an architecture standpoint. 14th gen is Raptor Lake Refresh on desktop and Meteor Lake on mobile, this means that on desktop from 14th to 15th gen there will be a 2 (3?) node jump. Edit: Oh well apperently they just said that Meteor Lake would come to desktop in 2024.
At the end of the day, only TWO things matter: Power & Efficiency. If you win the crown at the expense of HEAT...NO GOOD. If you don't win the crown...oh well. That's NOT GOOD. So U need to be FAST...and COOL!
I'm not the smartiest pant but wouldn't having a workload to go through the Low power island, then the E cores to then finally arrive at the P cores going to introduce significant latency?
Very cool tech, but there are problems they really need to solve. Weird latency issues with today's p cores and e cores, even though the p cores get the work first.
I hate dirty marketing tactics when companies change naming conventions like this. It's borderline false advertising. They wouldn't be doing this if they had 10 companies to compete against.
improving energy efficiency by addin another cpu inside the cpu. unless the mini cpu is arm based i don't know how an extra processor is going to improve performance. maybe it won't be used at all because its so weak. i wonder if there's going to be some way of testing only the mini cpu.
When you say tiles can be made by different foundries, does that mean, different tiles are glued together? Or the wafer is passed on to the different foundries??
Its different wafers from different foundries, they can use any node or foundry. Intel uses an active interposer (silicon) as the baseboard, that the tiles sit on and transfer data through. There is no glue lol. Its basically smart chips on top of a 'dumb' chip that connects the smart chips, but its far more technically complicated.
