Latches and Flip-Flops 3 - The Gated D Latch 

Quite literally the best resource on the internet. No unnecessary information, straight to the point, simply done, and animated. THANK YOU for this

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One of the best composed lessions I've seen

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Amazing explanation, simple words, nice animation, and informative video. Many thanks.

best video to explain D latch

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I finally understand gated d latches. Thank you!

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the enable can be used witha push button to alternate tue outs between 0-1 like a switch?

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Looks like the lines between the NAND gates should be red at t=91s. Am I wrong?

Great information! Than you for all the help!

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I really liked the first two videos, but this one is very confusing. One thing I don't understand is why this circuit is called a latch when it does not latch actually. The difference in its behavior is clear when compared to the previous video (#2). This circuit does not work with pulses (see 2:28). It requires that the D input is already latched/sustained in order to operate like the latch it is supposed to replace (gated SR latch). The output Q is latched only as long as the Set button (D input) is sustained. Up to this point, Q acts as a buffer for D without any latching properties. It doesn't only fix a problem of gated SR latch, it also changes its operation. Another problem I see in this explanation is the behavior of the E input which is a little bit different here. In the previous video, the role of the E input was only to enable or disable the functionality of the set and reset buttons/signal. In this circuit the E input has also another function. It can affect/change the output (see 4:19 , 5:58 and 6:13). Anyone care to clear up my confusion?

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I don't understand why when we have D=0 and En=0 we continue getting Q=0 . If I am correct , after the 1st upper NAND we get 1 and after the first down NAND we get 1 . How can we determine then that Q=0 ??? It isn't obvious from the logic diagram of NAND...Anyone help please ??

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2:29 Hey, shouldn't this only be an and gate, not a nand gate please? For the inputs, not the SR latch part

Excellent

what.. before you said the nand gated SR latch is active low.. because both S & R are always high..

That unpredictability could be useful in ways can it? That has the potential to be an A randomizer of sorts.

very informative,thank you.

can d latch only be with nand gates?

Thanks for the videos :)

excellent thank you!

extremely useful,tks

Can you show the Boolean expressions and talk a little bit about them

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What about the jk flip flop

Molto interessante, ma le tecnologie in inglese non è facile capirle