You're a life saver My professor doesn't know how to explain this very well Don't get me wrong, he knows his stuff But he just isn't good at teaching Thanks to you i actually got an A on the test
I've searched everywhere for better explanations on this subject, and I am so incredibly glad that I stumbled upon your videos. They are fantastic and I sincerely thank you for creating and sharing these!
Thank you thank you thank you, that was so simple and informing and you did a wonderful and great job demonstration l. PLEASE continue making these videos.
@@ComputerScienceLessons it's a shame i wasn't able to find a JK flip-flop video on your channel. Don't get why is supposed to be acting as a toggle at 1 1. The funny thing is that my teacher wasn't able to explain it to me :D
I really liked the first two videos, but this one is very confusing. One thing I don't understand is why this circuit is called a latch when it does not latch actually. The difference in its behavior is clear when compared to the previous video (#2). This circuit does not work with pulses (see 2:28). It requires that the D input is already latched/sustained in order to operate like the latch it is supposed to replace (gated SR latch). The output Q is latched only as long as the Set button (D input) is sustained. Up to this point, Q acts as a buffer for D without any latching properties. It doesn't only fix a problem of gated SR latch, it also changes its operation. Another problem I see in this explanation is the behavior of the E input which is a little bit different here. In the previous video, the role of the E input was only to enable or disable the functionality of the set and reset buttons/signal. In this circuit the E input has also another function. It can affect/change the output (see 4:19 , 5:58 and 6:13). Anyone care to clear up my confusion?
I don't understand why when we have D=0 and En=0 we continue getting Q=0 . If I am correct , after the 1st upper NAND we get 1 and after the first down NAND we get 1 . How can we determine then that Q=0 ??? It isn't obvious from the logic diagram of NAND...Anyone help please ??
Hi David. If you watch my playlist on DRAM, you will see that decoders and multiplexers are covered to some extent in parts 3 and 4. :)KD ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-I-9XWtdW_Co.html