Video discusses about LDO, regulator types, differences between linear and switching regulators, LDO working, both PMOS and NMOS and the differences between NMOS and PMOS LDOs.
In an open loop op-amp circuit, there is no concept of 'virtual ground'. However, in an op-amp with negative feedback such that it behaves as an amplifier, the inverting input maintains exact potential as that of the non-inverting input.
So if I understand properly, there are no oscillations in schematic simulations but after layout and parasitic extraction you are facing stability issues.. It's very difficult to point out without knowing more about ldo: architecture, current, compensation etc..
Very good information and excellent presentation style. I have one query... How do choose the specifications of the error amplifier? I mean how to budget the bandwidth and gain for the error amplifier?
Error amplifier gain is calculated based on your output voltage accuracy reqd. Bandwidth requirements of the amplifier depends on overall stability of the LDO and response time of the LDO..hope this helps
Great video sir, i had one doubt , in nmos LDO when vref and feedback voltage is same the output of opamp becomes 0 and vgs is either 0 or -ve depending on the predefined voltage at output. So will there be any offset output voltage added just to turn on the NMOS. Correct me if i went wrong anywhere.
in NMOS LDO when vref and vout are same; 1. resistor divider is not required. 2. The output of the opamp should be greater than output voltage by one Vth. suppose, Vout=1.25V, (equal to Vref), then the output of Opamp should be Vout+Vth of NMOS; i.e. 1.25+1V (assuming Vth of NMOS=1V). Hope this clarifies.
@@analoglayoutdesign2342 ,thanks sir that was very insightful. Sorry for the bad format of question formation. My question being reiterate 1)when vref=vfedback (considering virtual short) the opamp output to gate of nmos would be 0. Since for nmos vgs to be positive , won't the nmos be turned off?.
Ok if vref and vout are equal, then a.c or small signal output of opamp will be zero. But large signal or DC levels will still be maintained by opamp output. Hope I answered.
Hi, in the slides I will not put in full information. I will write on it and explain. So please go thru the video by pausing wherever required and my suggestion is to make some notes. This is what I do when I listen to lectures. That way it will be very useful. For downloadable material, there is quite a lot of material and app notes from all product companies. That will also help.
Hi sir. I have two questions. 1) How do you calculate the W/L ratio accurately of Pmos pass fet for a specific load current. 2) What is the main contributor to set the output voltage, error amplifier or resistor divider?
1. Decide whether you need passfet in saturation or linear. Generally saturation so that we get gain. Keep L min. Now u know current, vds, kp... So calculation is straight fw... 2. U can use both. When you change the reference voltage, output voltage will change accordingly. The error amp should have that input voltage dynamic range. But to get voltage reference which varies linearly is difficult. Resistor divider should have resistor bank to program the output voltage. Here the quiescent current will change when feedback resistor value changes. Hope its clear..
Hello sir, In nMOS LDO case i have some concerns that i have learned that nMOS works in saturation mode when Vds>Vgs-Vt. In your example, Vds=3.3-2.5>3.5-2.5-1. It seems like LDO still works with Vdd=3.3 in case Vg is not greater than 4.3. If I have any mistake, please correct me.
In NMOS LdO, NMOS stage is in common drain configuration. Let’s say vin=3.3, vout=2.5 and Vt=1v , then gate voltage should be vout+vt at least I.e. 2.5+1=3.5 Question now is where do I get 3.5v which is higher than supply of 3.3v…vin and Vdd are same…
Hello sir, thanks for the great video. Got 2 questions: 1. if Vin-Vout = V drop_out, at 35:43, V drop_out is 10-3.3=6.7V, then how come the drop out voltage is 3.6V, and later it becomes 3.6-3.3=0.3V? which one is the real drop out voltage? 2. Why when Vin is under 3.6V, the error amp won't work? Looking forward for the reply. Thank you
When the current increases suddenly, the pass element cannot provide so much current. Current is provided by load capacitor. When charge(current) is removed from Capacitor, it's voltage reduces.. which is nothing but output voltage... hope this answers
That’s true. NMOS pass element when used with lesser difference between Vin and Vout, they use a charge pump to boost the supply of the amplifier driving the pass element.
