#32 Linear voltage regulators architectures 

NMOS regulator needs gate voltage higher than output voltage. Since threshold voltage of nmos is ~0.7V, I have assumed we would need 1V above vout.

For most part nmos and pmos work in saturation. For higher load current pmos may enter linear but a good design would try to limit it to corner cases. For nmos if amplifier is supplied by vin then nmos will always be in saturation region.

Infact there can be benefits in PSRR if you use the source follower LDO

@@yunusdification only if you have very good PSRR for your Amplifier. On other hand for PMOS LDO amplifier PSRR should be ZERO

@@vladimirvolokitin8367 yeah good point. the first pole of opamp becomes the dominant pole. So in fact to adjust that pole you add cap at output of opamp to compensate the loop. This cap should also help the PSRR.

What do you mean by digital ldo? The use case that I gave in video?

@@analogsnippets No. Loop will be digitally controlled with power mos acting as switches.

I have only read about it, not actually designed it. So not an expert on this topic.

Hi Pikul, here is a link to a simple work we did for dig ldo: A. Lahiri, S. Bansal, N. Bansal and M. S. Hashmi, "Digital LDO with analog-assisted dynamic reference correction for fast and accurate load regulation," 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, pp. 767-770, doi: 10.1109/MWSCAS.2017.8053036