LMARV-1 reboot part 8: Exploring layout for multiplexed registers 

Thanks for the christmas present! I was wondering when I was gonna get my RISC-V fix ;) Happy Holidays! :) Also, how many of you tried to zoom in on the schematic ? :P

you get my best channel on youtube award.

Awesome project! I think staking the boards is the best solution. You could use a card edge connector in addition to stand then up on a backplane.

Another solution for your clock enable register would be to use a different clock. Instead of using one that pulses, you could use the clock that the pulses are derived from. Then you could gate it with the enable signal. However, using a re-direct mux is much safer as you said - I believe that's typically done in silicon as well. For the headers, you should be cautious... 2.54mm headers can bind very easily... First of all, a 4xN connector is a huge pain to use for anything other than small quantity Dupont connectors. So you will want to stay away from 4xN (2xN is more manageable). Second of all, the longer you make the header, the harder it will be to use (the Raspberry Pi is pretty much pushing the limits at 2x20). Third, it will be almost impossible to connect a card that spans all 6 buses via 2.54mm headers... you will probably have to plug the headers in before soldering, solder them to the board, and never remove it... Perhaps you should consider looking at HMC connectors? The Raspberry Pi CM4 uses some cheap ones DF40HC(3.0)-100DS-0.4v. Those are 2x50 and much easier to plug in since the contacts are shorter. In terms of return paths, I wouldn't worry too much about that unless you start to see noticeable noise with an oscilloscope. As long as your signals are below 50 MHz you can probably have up to 8 of them in a row without a ground between them. Practically speaking, that's probably more like less than 100 MHz and 16, but 50/8 would be safer. The whole reason the 74 logic has gnd-2-gnd-4-gnd, is because of the die inside of the package. That's a function of power new connection requirements on the die and layout (i.e. they may need 3 ground pads and only have space to fit them on the ends and between the signals). Then the pinout on the chip is arranged so that the bond wires don't have to cross each other (which can risk an electrical short). So I wouldn't make any assumptions about the signal layout on the chip except for the case where you have GHz speed signals. If you look at QFP FPGAs, they have more than 4 adjacent signals and expect signal speeds upwards of 100s of MHz. You probably shouldn't be routing with 3.5 mil traces. It's likely that many of the boards will fail during production (since that's the minimum capable width / spacing). Also, 3.5 mil traces won't be able to carry much current and will also have a high resistance / length. I would have started with at least 5 mil, and since you are connecting to a bus which will have to drive more current (10s of mA), you should probably do 8-10 mils. You may also want at least 2 power pins - you may want to do a power budget for the chips to see how much current they could draw. A few ideas for the sequencer control array. You could probably use SRAMs with an initialization cycle from a ROM (if I recall correctly, you did that in your last iteration). You could also use a small QFP FPGA or CPLD (like a Max 10 or Max 5) which is purely being used as a fast ROM (I don't think that would be cheating). Keep in mind that older computer systems did use PLAs instead of discrete logic for complex logic equations - you could also use PLAs, but those would be a pain to work with. Anyway, looking forward to the next video.

It's time to write an FAQ. Possible subjects: 1. Why gated clocks are a bad idea. 2. Why nmigen instead of VHDL/Verilog/.... (religious argument) 3. Why hand-generation of HW schematics instead of auto-magical RTL-to-74xxx converter 4. How to write nmigen code (see the tutorial) 5. Why not use an FPGA (see title of project) 6. Why not use unit tests (see formal verification) 7. How to load (package referenced in video) 8. Windows versus Linux versus Mac (another religious argument) What other subjects seem to come up time after time from folks that don't bother looking through the long history of videos before asking questions?

Come to the metric side Robert. It's just better in every way :). Marry Christmas by the way.

for those 4 chips on the left, It would be simpler (for layout and PCB traces) if the buffers were aligned in the same way as the others, and the registers were placed inverted and (slightly) offset on the _opposite_ side of the PCB (the bottom). This would mean the bottom layer would have (super) short traces (with vias) back to the buffers on the front side, _and_ they could be placed out of the way of the buffer traces to the bus. Electrically this would be better (for the traces), as all register to buffer traces would be (approximatel) the same length, and (extremely) short (compared to the buffer to bus traces). The only issue I see with this would be in fabrication population, ie can the manufacturer do this, or is it an extra (large?) cost. I dont see a problem with stacking, as (shown on RPi) there are various height bus extenders (if inter-board chip proximity were to be an issue, say for heat (airflow?) or access (testpoint?) ). One last thought - if the chips are SMT, then wont that cause an issue for the placement of (currenty unplaced) trace capacitors (based on the current trace layout)? However, if they are socketed, then there _is_ room for them under the chips.

You probably should use bigger tracks by default. Using these tiny traces will probably be very fragile, cause higher resistance and more interference than necessary and make manufacturers like JLCPCB unhappy because they'll likely have a high percentage of boards that fail the test and have to be manufactured again. For example the PCIe standard recommends 5mil tracks with at least 7 mil gap in between their signal lines, and while PCIe is probably much more sensitive, I don't see a reason to go below that.

For the sequencer, instead of ROMs use some fast SRAMs programmed by a GAL from EEPROM at startup? More points for using a single large serial EEPROM. Might be overkill but I imagine preferable to unchangeable logic. Would the sequencer itself fit in a GAL? Unsure. Very interested to see how the HDL will be changed to represent the "chip design" however it's done, especially for this part. Stacking boards is a fantastic solution. Or rightangled 0.1" headers though you'd need some kind of card frame. Also, do you need power on your 48 way headers or is that coming from somewhere else?

have you thought about PCIe connectors with small adapter boards connecting them vertically. tho through hole might be better for stacking more boards

be careful with track width and track distance, you may need 0.9mm and not 0.0889mm

14:35 I'm not sure the datasheet says that disable time is always shorter than enable time.

Ctrl+Enter activates the OK-button in a lot of KiCad dialogs [2c] Why not put the chips on both sides of the PCB? Are you gonna hand-solder them?

I would think the next board layout that connects to that is going to be a mess. What about having a single register card that fits in a vertical laptop DIMM socket and then having a array of them? This would give the next board more flexibility as to where they are placed. Just thinking smaller connectors. edit: but then again that makes the multiplexer more complicated.

Just a random thought regarding the system clock - since it's distributed to pretty much every chip on every board, are you expecting to need to buffer it on each board's input, due to line loading effects? P.S. just noticed your "ALAN: In space nobody can hear you space" t-shirt. Got the same one :D

Did you check JLCPCB SMT assembly? This could make your life way easier, especially if you need the same board multiple times like for registers. They have a lots of 74-series chips that can be assembled. Unfortunately, they do not assemble connectors yet.

1:05:25 squozen

What about the 47k resistors instead of REG_PC? You save the space, you save the control signal... If the mux opens it overrides input value, otherwise the register output is loaded on the clock edge

Is it much of a worry if two outputs are enabled at the same time for what would be just a couple of nanoseconds? The value that has been output isn't going to be needed for 10s more nanoseconds so it will have plenty of time to stabilise before being clocked into anything else.

"this board is 75 millimeters, so we are talking a meter wide board" 75 millimeters is like 3 inches. 75 millimeters is 7.5 cm and there are 2.54 cm per inch. 2.54 is roughly 2.5.

It looks too big. It will need 0.4mm b2b connectors and passives on the bottom side... 4 layers will be enough for it

I'm late to the party, but can I ask, why not just make it into a cmos package? The whole thing (all registers, mux, everything) can fit into 1 chip. I'm only asking because printing out those circuit boards and taking up that much space will cost more than just doing a litho and pack. This game is amazing and allowed me to perfect my cmos skills: www.zachtronics.com/kohctpyktop-engineer-of-the-people/

connect with ribbon cables and stack the boards using a dvd rack, then you're COOKING