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Nandland Go Board Project 3 - The Flip-Flop (AKA Register)

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The third Nandland Go Board Project. Learn about the second most fundamental component inside an FPGA: Flip-Flop (or Register). Flip-Flops allow your FPGA to have a concept of State. They allow the FPGA to know what happened previously in time. Flip-Flops require a digital clock, which I introduce in this video. This project toggles the state of an LED when a button is released.
For the text version of this video: www.nandland.c....
For the Clock Constraints (.SDC File):
www.nandland.c...
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/ nandland

Опубликовано:

6 сен 2024

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Комментарии : 46

@megha3678 7 лет назад

Thanks for creating these videos. The concepts are explained very clearly.

@farhanyousaf5616 2 года назад

Just bought your board. Looking forward to playing with it.

@Jocjabes 4 года назад

@18:57 for every clk posedge, r_switch_1

@jamesmccoy8568 4 года назад

Sounds like you are thinking like a software person. I was confused at first as well because I’m a software person. In those if statements r_switch and i_switch are not yet the same value. We are effectively checking the value of the register before we set it, because the value check happens before the circuit has had enough time to assign to that register (r_switch). Correct me if I’m wrong, that’s my understanding at least

@Ashers370 6 лет назад

The if statement never get's true... Shouldn't you move the "r_switch_1

@moop857 5 лет назад

Yeah, you're right. I don't get it either. But it works. Both works, before and after the If_Block. Don't know. Maybe somebody can explain it to me, pls

@nxxxxzn 5 лет назад

It's explained here www.nandland.com/articles/blocking-nonblocking-verilog.html

@marcomoldenhauer7903 Год назад

Hello Nandland, at time [31:01] in the video I have a different result. First in my case there is no "SB_DFF" shown and second "SB_LUT4" is "0 uses". Can anybody help? Note, that I added the verilog file. THX and BR Marco

@marcomoldenhauer7903 Год назад

I could solve this issue by myself. Now I used the vhdl code (as it is demonstrated in the video) instead the verilog code and it works :) But it should also work with the verilog code right?

@DanEllis 4 года назад

Why can't you use "if falling_edge(i_Switch_1)"?

@ToniVarga 6 лет назад

Awesome video..had some trouble wrapping my mind around nonblocking statement, but now I get it I think :)

@darronvanaria2952 Год назад

If the code in the sequential block (the always block in verilog) gets called every rising edge of the clock signal, how often does the combinational logic get called (all the code outside the always block)? Isn't is also tied to the system's clock? Does it called more/less frequently than a clock cycle? Or maybe that's thinking too much like software programming. I guess the combinational code just sets up the hardware, and it is always "running", so it reacts instantly to any changes on input lines...

@Nandland Год назад

Combinational is always "running" yes. It's wires, LUTs, you can think of it like gates. That information propagates "instantly" down the wire. Totally different way of thinking about code :)

@klong4128 4 года назад

Very inspiring using hardwareFPGA + Verilog/Vhdl softwares Programming . I recalled 15 years ago when I first Self-training Arduino . Now Arduino becoming a Primary school Training Kit .Similarly when I first Self-training FPGA 5 years ago (gaveup within 3 days) .Your video inspires me after looking at your first 3 videoes .Now I understand 95% of Fpga. If I intend to use it heavily in future, I will comeback to nandland.com .And fully learn up within one month . Hardware of FPGA can learn up within 24hrs .Only the Software need one month's to learn up to the expert level due to programming technical words/library commands . Thanks for your inspiration and enlighten my Deep-mind . Thanks again sharing out knowledge to everyone . Please don't follow Trump Selfish dirty politic idea that intend to Kill-opponents and end up self-killing himself indirectly !!!! Thanks again helping others will help yourself in return .

@user-gj7kn1sv9e 2 года назад

do these codes work for vivado verilog?

@almostcute 2 года назад

Hi! great tutorials thx. My Go board is on the way to me and I look through videos in advance. I'm wondering is there a way to automate FPGA building pipeline. So one can work with it without GUI. It would be cool to have CLI commands like add design files, add constrains, run all etc..

@alamuru420123 7 лет назад

Thanks for making this video. It's very detailed and explains the concepts very clearly! After this video, I started thinking that D Flip Flops are probably used everywhere there is a memory element with a clock input. For example 8-bit shift registers (74HC595) and the Decade counter(CD4017). Is that correct?

@tetsujin1977 8 лет назад

Dear Sir The file I am talking about is the "Go_Board_Clock_Constraint.sdc" (which is the one that controls the clock speed) not the "Go_Board_Constraints.pcf " (which allocates the pins), is the ".sdc" file provided separately by you through a certain link? . Thank you very much for your quick responses and dedication.

@Nandland 8 лет назад

The .sdc file is available here: www.nandland.com/goboard/Go_Board_Clock_Constraint.sdc Sorry for the delay in getting back to you!

@alirio128 7 лет назад

Hi, I'm trying to add the clock constraints to the synthesis process. However iCEcube2 seems to insist in using afile called Clocked_Logic_temp_lse.sdc which uses a period of 1000. It seems not to matter if I add your clock constrains to the synthesis or the p&r constraint files or at all. Only entries made by Timing Constraints Editor tool seem to be respected but I end with two clocks in the report. Any Idea why that would be? (Linux Mint 17, iCEcube2 2017.01.27914, Lattice LSE Synthesis) And thanks for your amazing work, its a pleasure to learn on your system!

@Nandland 7 лет назад

Thanks for the compliment! Interesting, I haven't seen that before. Does the clock name match the name in your design? What if you edit that Clocked_Logic_temp_lse.sdc file? This might have something to do with the fact that you're using LSE rather than Synplify. Perhaps the formatting is different for the LSE constraints. I would suggest looking up how the .sdc file that is created automatically is formatted and compare the two. Let me know if you get to the bottom of this!

@alirio128 7 лет назад

Hi, I figured it out, had a malformed .sdc file (instead of copy pasting yours I wrote it myself for learning purposes). It results that Lattice LSE Synthesis does not complain about malformed create_clock statements and just takes a default value to work with.

@Nandland 7 лет назад

Thanks for the update, glad you figured it out.

@indyzd 6 лет назад

I tried this with the exact same code, but the LED always stays lit no matter what. I tried recompiling the code to use i_switch_2 and o_LED_2 and its doing the exact same thing. Is there any reason for this? I can't figure out why its happening

@Nandland 6 лет назад

Couple things to check... make sure capitalization is correct, Verilog is case sensitive. Also double check your pin constraints file (.pcf) is correctly loaded in your project and matches the Verilog code. This tells the tools how to map the design to the physical FPGA and is very important.

@theDarkBrainer 7 лет назад

Awesome tutorial. I'm a software engineer and i really like working one level down :) I'm struggling to understand the meaning of the 'process' inside the architecture. Am i correct in thinking that the logic defined in the architecture is the direct connection between the entity ports, where as the 'process' is something that is triggered only when the sensitivity list changes (upedge or downedge)? I'm confused about the sequence, which one is first ... or even if 'first' is meaningful here. But it must, as one uses data from the other.

@Nandland 7 лет назад

This might be a good post to read. www.nandland.com/vhdl/tutorials/tutorial-process-part1.html In short, process only is executed when sensitivity list changes, yes. Everything happens all at once inside an FPGA (on the rising clock edge). It's a strange concept and totally foreign coming from SW, but you'll get used to it the more you work with it.

@theDarkBrainer 7 лет назад

The example @27:58 of the video. The i_Clk drives the Flip-Flop which Q ties back to r_LED_1, so there is a feed-back loop i guess created. Also, the architecture uses r_LED_1. So, the process in this case is a loop back from r_LED_1, which will be changed by the process and then the signal will get propagated to o_LED_1 due to the code in the architecture.

@theDarkBrainer 7 лет назад

is there a tool that can visualize the logic wire diagram that is created from the code? It would be helpful to visualize the code in terms of electrical connections.

@Nandland 7 лет назад

Synplify, which can be opened with IceCube2.

@laszlobertapercy5210 6 лет назад

in VHDL @ IF section, could i use " r_LED_1

@Nandland 6 лет назад

Try it, but I don't think that will work, otherwise the LED will be stuck ON all the time.

@MrSapps 4 года назад

@@Nandland it would work if it was set to 0 outside of the process or in an else block ?

@tetsujin1977 8 лет назад

Dear Sir Is the "Go_Board_Clock_Constraint.sdc"file provided by you? if so where to get it from?

@Nandland 8 лет назад

It's this file: www.nandland.com/goboard/Go_Board_Constraints.pcf It's a PCF file. So add it to your Place and Route constraints and it should work for you.

@CraigHollabaugh 6 лет назад

Got a newbie sequential question, are all the statements in the always block executed simultaneously on i_clk? They're not actually executed sequentially like CPU code. Thanks

@Nandland 6 лет назад

Yes. They're all executed simultaneously. The one exception to this is using blocking assignments, which in general I don't recommend doing as a beginner. Here's more: www.nandland.com/articles/blocking-nonblocking-verilog.html

@CraigHollabaugh 6 лет назад

Thanks, I'll take a look.

@xmotoFF 7 лет назад

Hi Russell, do you know how to incorporate the .sdc file in the IceProject flow? I haven't been able to find the answer.

@Nandland 7 лет назад

Hm, I'm not sure. And if you've looked unsuccessfully then I'm not sure I'll have a better shot. But you don't REALLY need the SDC. As long as the pins are correct and your pcf has the clock information you should be fine.

@xmotoFF 7 лет назад

Yes, it worked!

@dimovnike 8 лет назад

Hi, is it possible to use the i_Switch_1 instead of i_Clk and skip the code that checks for previous state of the switch? I.e. use the button input as clock. (just trying to understand it better if FPGA can work with a "dynamic" clock). Thanks.

@Nandland 8 лет назад

+Nicolai Dimov that's not a good Idea. Essentially what you're describing is creating a latch. Latches should be avoided especially for beginners. The best way to avoid latches is to only use sequential processes (always blocks in Verilog). Definitely keep a clock!