1:55 there is a ferrite bead used on a pi filter at the input of the regulator. same time, Zach peterson have made many videos about never use ferrites, both are in the same youtube channel. make a decision please :)
This looks more like what you need - Power Integrity Analysis Using Ansys SIwave - It gives simulation of Z parameters for use in things like transient analysis. This is more like a real PDN analysis for getting impedance for switching sources (DC-DC/SMPS) and the source impedance of the network for the switching loads.
Hi Phil, cool video. I just tried PDN Analyser 3.0. Is there a way to simulate the temperature of the copper? I have a high current multilayer PCB with 15A. And I am interested in the temperature distribution. Thank you, Andreas
You can roughly gauge temperature from the resistivity of the copper. Generally you’ll want to look at the hottest region and make sure that’s within your board substrate spec. If you need to simulate temperature flow you’re going to be staring down a very, very expensive license for dynamic sim software that takes into account ambient room temp, airflow, etc.
When I clicked on this video I was really hoping for a more in depth analysis like I'm used to by Zach's videos but it turned out to be 11 minutes of GUI setup, and 2 minutes of DC analysis on a board where current density is really not that high and thus IR drop is really not that important. It would be much better if the actual DC analysis comprised a more prominent stage on the video (instead of just a small portion of it) and if it was done on a design where it actually mattered and showcase how do you solve an actual problem that would be otherwise very difficult to do so without this tool (e.g. a very high power board like a power supply and see how you adjust the layout based on the feedback from this tool).
Thanks for your feedback. Completely agree - and this will be covered in a further video, as this one is simply meant as an introduction to the tool, and how to set-up a simulation. I have some fairly high-current FPGA designs, as well as an ESC design that I'll be demonstrating with the help of the PDN Analyzer, then showing techniques for (fairly) high-power layout and routing.
amazing video, again. Is there a follow-up video to this? I was also hoping to hear if an of the "highlighted" areas might be problematic and what philip would suggest to remidy them. Any suggestions for follow-up / deeper pdn videos?
This is not really a PDN analyzer - it does NOT provide what a PDN analyzer SHOULD do - provide the IMPEDANCE (that means AC components) NOT just simple DC. Until this does IMPEDANCE analysis, it's only good for stuff like simple static DC components like resistors and LEDs. I mean the cute little histogram looks cool, but that's not a true representation of what's actually going on. To do a REAL PDN analysis would require something like 3D field solver/FEA I'm not making LED boards with just simple LDO/Linear regs. Typical digital systems utilize SMPS and switching loads. THIS is what determines the impedance requirements of a PDN - real any trade mag or text book on PDN. Z_PDN=∆V/∆I Those Delta symbols mean a lot... "If we take a closer look at the frequency behaviour (see Figure 2), it becomes clear that any PCB power delivery network will show some degree of capacitive behaviour at lower frequencies while this capacitance decreases due to the resistance of the power-bus in series with all the load components and its return path and then the inductive behaviour typically dominates. Figure 2 shows all impedances vs. frequency for a NXP iMX55 CPU for a DDR3 power rail of an automotive ECU for all the CPU power pins. The impedance is affected by the physical separation within the power rail in the board stackup. As frequencies increase, the mutual inductance between the different circuits on the board will cause the impedance of the power distribution network to increase. Due to various effects, the impedance of such a structure shows many peaks (resonances and anti-resonances). At higher frequencies, the impedance often negatively influences the input behavior of the ICs, which is highly undesirable especially in the frequency range in which the ICs are supposed to operate." There you have it - REAL PDN analysis. The reason that uC datasheets don't show current consumption is due to the switching varies as the part is configured and run. AGAIN - an AC problem not simple Edison DC stuff. Tesla won, Edison lost... simple... See TI's app note SWPA222A which states: "To complete the PDN analysis, it is necessary to determine the target impedance of the overall power net. Target impedance extraction is achieved using the Frequency Domain Target Impedance Method (FDTIM ).and the objective is to maintain the target spectrum below the Z target value (Z target ) from DC to F max . The Z target value is determined by: 𝑍𝑡𝑎𝑟𝑔𝑒𝑡= 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑅𝑎𝑖𝑙∗ % 𝑅𝑖𝑝𝑝𝑙𝑒 0.5 ∗ 𝐼𝑚𝑎𝑥𝑡𝑟𝑎𝑛𝑠𝑖𝑒𝑛𝑡 F MAX is the point in frequency after which adding a reasonable number of decoupling capacitors does not bring down the power rail impedance |Z EFF | below the target impedance (Z TARGET ) due to the dominance of the parasitic planar spreading inductance and package inductances." Cummon guys... get it together... Provide us with a real PDN analyzer BUILT IN to Altium.
