Plot IDS vs VDS for the circuit : Interview question for "Analog Circuit Design in a MNC" 

Hi Praveen , thank you for pointing out. There is a correction needed in the last part of the graph. *For VX > 1V , Vx will be the drain , So VGS will be 1V and the mos will be on . Under this condition , for VX >=1V MOS will be in saturation. *For VX=1V IX=0 , VDS=0 here. *For VX < 1V , Vx wil be the source , under this condition , as rightly pointed out by you, we are at the edge of saturation. So for VX

@@vlsiorg For Vx>1, the MOS is in saturation, but (Vgs-Vt) = 0, so by the square law, Ix should also be 0

Hi. I am not use if i understand your question correctly. For VDS > 0 and Vgs-Vth =0(saturation) . There will be current . You can also look at it from the I-V curve perspective . Thanks

Hi vishal , i have written the correction in the comments. I will soon make a update on this in my next video. Thank you 😃

@@vlsiorg since the gate to source voltage is not more than threshold, will there be any current. That's my doubt