Sometimes I fantasize about buildzoid coming home drunk and beating me until I feel numb. He kicks me in the ribs until I can hardly breathe. Then he starts to cry and apologizes, begging me to forgive him for calling my timings atrocious. He holds me all night as I gently cry into his "keep calm and raise vcore" t-shirt.
That beginning rant though...BZ sounds like the disappointed parent that catches you coming in at 2AM drunk beyond reason, and just looks at you saying "I'm not mad, I'm just disappointed" LOL Good stuff as always
BZ, I appluad you. You give us all the f*ing cookbook to overclocking fundamentals and all the protips that takes countless hours of testing to know. Amazingly people give up halfway through. and if you made a Zen3 + BDie video it'll rake the views. I guess the masses don't want Hardcore or lengthy in depth video breakdowns. Anyway keep it going :)
What would explode views would be literally 1 single picture of memory timings like in this video at the beginning, walking through every single timing explaining what it does
I def get more out of the ram oc videos after watching the ram timings series. Recommend ppl at least watch the last one, that was where it clicked for me. Tho I still suck at ram overclocking lol. Good rant. It makes me wonder in what ways and xpo profiles will be different from Intel xmp
"Newer AGESA doesn't spit out F9". Latest Asus Dark hero does, I had 6 of them last night whilst tuning RAM... in all cases it was trying to push the clock beyond 2000MHz. My IMC won't go even 33MHz above it, no matter the voltage. Also, as much as this video is partially unnecessary (I watched the previous videos), it's a good focus topic that really needs to be better understood by anyone tweaking memory.
Absolutely appreciate these videos. This is literally the first time I'm starting to understand all these timings. Does take a while to get used to all this and get all the different timings in my head. These practical examples help a lot. It's nice to finally know what I'm doing instead of just typing in whatever comes out of ryzen dram calculator ;-) Also love the rants haha. It's not super complicated but it is a LOT of information to absorb. So it takes some time haha
tFAW to 16 I remember that. That is the timing that limits how fast you can send 4 read commands. For the others I'd have to rewatch your videos a few times, keepign all the acronyms straight is hard. But cheer up, I at least learned and *retained* at least a bit of information.
TLDW: tune tRAS second to last and tRC last so it won't mess with your other timings. They also won't do anything if they are lower than your tRCDRD/WR and tRTP/WR combined for tRAS or tRAS and tRP combined for tRC. Just like tFAW won't do anything if it's less than four times tRRDS.
Memory timings have realistically changed very little over the years and most come from a time when memory was accessed through actual strobes, some could be depreciated but jedec seems to keep them for fun. On older memory Tras was the number of cycles that the ras pin had to be held high following a row strobe. As far as the activate -> precharge with no read or write, this can happen, it is the basis of rowhammer attacks.
Dear Mr. BZ, try not to be so impatient: if its taken you years to put out a series of videos on a requested topic, do allow your viewer base sometime to watch and subsequently absorb the information therein, the latter of which may take several review sessions for the viewer. If someone is asking you a question on a topic you've already addressed on AHOC, perhaps you could be so kind as to direct them to your channel rather than berating your entire viewer base for being idiots, as entertaining as that is to watch! Rant over, cheers.
Buildzoid should be a teacher. You literaly knew I watched previous videos and thsu I clicked on this one to continue the logic trail... and you slapped me into face for being idiot for not paying attention previously and even laugh into my face. In other words, the perfect motivation.
Well, im a big dum dum when it comes to memory overclock, thats why i subbed to you. Your timming videos helped me a lot to understand why timming is there and what for
"You know, it just so happens that I have a video for that. That video also just so happens to be part of the same series this is in, and just so happens to have an index number in the title for where it is in the series." I find it as baffling as I do disrespectful that people will skip videos in a numbered series and then complain about not understanding something. Just *why*.
GDM on you can set any timing as low as possible. but GDM off and 1T, some timings you have to follow their "rules" or it will go bsod. but I already tire to tweak any DDR4 kit. new DDR5 is the revolution.
The thing is if you have the wrong row open you end up taking longer getting to the correct row if it's in the same bank. Since instead of just needing a tRCD+tCL/tCWL you need tRP+tRCD+tCL/tCWL. It's also possible that AMD does speculative row activations but is just much less aggressive with PRE commands. Intel CPUs seem to be able to send PRE commands before tRCD is over.
Buildzoid, i would like to watch an analysis about current z690 motherboads power stages vs next gen raptor lake cpus, since 13900k is gonna be compatible with z690. All this to solve this question: do we need an overpriced new gen z790 motherboad to properly run an overclocked 13900k, or, is a mid-high tier z690 mobo capable enough? Also, your videos are amazing, i've learned a lot!Thanks!
That seems fairly unlucky. Are you sure it’s the 3950x and not other things like soc voltage or something else? When I was tuning a 3700x it easily hit 3800 and had a little bit more room but left it at 3800.
Could this be board specific? I have asrock b450 itx + ryzen 3600, my kit runs with 16-17-17-30-50 but I can't boot with the timings 16-17-17-33-45 for example. Trtp 6, twr 12, tcwl 14 btw. Am I missing something?
Favorite energy drink? Also regardless of the why, this video is great there's nothing wrong with giving this its own segment/video, I mean how many people actually know this even on OC forums lmao so it's a good (maybe even concise) reminder. I also agree with how tRAS shouldn't be there even a dumb dumb can notice how it pretty much does nothing for performance (magic formula), based tRC tuning.
Yea but does it guarantee you any speed/latency boost in real world? Edit: thanx for thorough explain of how timings work man♥️♥️♥️ i can finally tighten my crucial ballistix max to the absolute stable max ♥️
feel like i was spanked for being stupid... even though i haven't asked any question and didn't even finished watching timing videos, bcs i have rly cheap b450 mobo with 4x8gb 3200cl14 b-die with it and can't 100% stabilize it even with a bit looser secondary and therthiary timings, system pass all tests but sometimes randomly reboots, CPU is 5600x with +200 pbo, mobo is msi Mortar Max
I was under the impression that tRAS was the time that the RAS signal was asserted, and therefore could be ended before the precharge starts if it was shorter than the RCD+CAS combination for the respective operation. Once the RCD completes, the selected row should be loaded into the row buffer which means the RAS signal is no longer needed to connect the row with the row buffer/sense amplifier. The behaviour of this aspect might be the reason this demonstration does not work on intel.
Where is this mentioned because literally all the documentation I've read only talks about tRAS limiting how soon you can send a PRE after an ACT or how soon an automatic precharge can start. tRCD handles moving the data from the memory array into the sense amplifiers.
This was kind of true 25-30 years ago. Tras was "RAS active time" and was the number of clocks that Ras had to be held high after the row strobe but has changed with more modern memory standards. This is one of the issues with alot of the memory overclocking information that is available online, there is quite a bit of decades old, outdated information mixed in.
@@ActuallyHardcoreOverclocking I think it is implicit because under JEDEC, tRAS is way longer than the minimum of the RCD+CAS combination so it is gating when the precharge can start. It's only when you lower RAS below JEDEC values that RCD+CAS can become the larger of the two. tRCD handles the time that is needed to pass before the CAS is allowed to start, but because CAS and RAS are independent signals, for a read operation you can keep RAS active as long as you like once the data is in the row buffer. For a write operation RAS has to be held active anyway to push the data from the row buffer back to the row in the memory array, so RAS is held active until the precharge.
I'm sorry Buildzoid this video is still too wordy for me. Could you turn this into a TikTok series full of B-roll animations, maybe add a musical bit? Thanks xxoo lol
hey buildzoid, i have 4x8gb 4100mhz (b-die) adata, and i cant get it to work more than 3600mhz (also mobo spec says max for 4 dimms is 3600mhz, 2 dimms work perfectly on 4100mhz) board is asus prime x570-pro. tried lot of stuff, even with auto clocks nothing works even 3800mhz. is there anyway i can go around???
Your motherboard is daisy chain topology, therefore you shouldn't be using more than 2 sticks of RAM if you want high RAM clocks. With daisy chain and 4 sticks, the RAM traces will differ in length, causing extra instability. You want a T-topology motherboard for 4 DIMM configurations.
I like your content but it's hard to watch your videos cuz you get off on tangents and talk for a long time on things that aren't particularly relevant
Even stupid people like me could learn about timings if only the right information was available. What you would need is: 1 A list with all the commands. 2. The (simple) math behind it. 3. Why the math is like that (which is also simple). But unfortunately no overclocking guide or RU-vid channel will tell you this and googling doesn't give the right hits either. You all think BZ is such a genius, but you just spend 20 minutes on only 2 commands, which could be explained in less than 20 seconds.
