I learned about voltage double when I was in high school. I dismantled a TV high voltage circuitry to find out how the high voltage CRT worked. This was an amazing lecture. Something I was looking for a long time. Amazing. One negative thing is the application given at the beginning. It would be much more efficient and cheaper to mutiple the wiring of the receiver winding to increase the voltage needed to run RFID. In fact, it is done as a part of the chip design. Remember you loose about 0.6 volt for every diode.
The location on which the voltage doubler charges the output to increment of Vo/2 is supposed to be the time at 0V (but not at -V0 of Vin). In fact, the voltage doubler follows fibonacci's sequence because it reduces the time in which D2 remains ON by half each cycle.
Yes, you're correct. -Since after the 1st cycle of Vin, C2 attains voltage V0 at output, as such the n-terminal of D2 is now at voltage V0. -Therefore, to turn D2 on, the voltage at its p-terminal must be > V0. -Now as C1 has already charged to V0 during the falling edge of 2nd -ve half cycle of Vin, thus Vin pushes/raises the voltage at the +ve plate of C1 (i.e p-terminal of D2) only when Vin passes 0V. -Now since voltage at the p-terminal of D2 is > V0, diode D2 turns ON and C2 gets further charged by V0/2 volts while correspondingly C1 gets discharged by V0/2 volts. -In the next cycle, D2 will turn ON at Vin = V0/2, then in the next cycle at Vin = 3V0/4, and so on, due to the increasing voltage at the output (i.e across C2 after each cycle of Vin), which has to be overcome every cycle to turn ON the diode D2.
I think the capacitor charges through the probe scope so you only get Vin=Vout for point number 2 for a discharged capacitor and just for the first 1/2 second before the capacitor charges using the scope probe to complete its charge circuit and Vout goes to 0.
To complement this lecture, I recomend to see this link "ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-DI8Yt1AQrH8.html", that shows the simulation of the voltage multiplier just like the one explained by Prof Razavi
In limiter at 13:05. When the input voltage is positive greater than Vdon the output voltage measured at D1 will be Vdon but at D2 whether it will be Vin?. So will the graph be different from which you showed?
Sir in voltage multipliers observation point 4 how the voltage across the diode increases as the input voltage increase ???The capacitor only will be charged untill it reaches maximum ..
Sir in one of your previous lectures you mentioned that we cannot say voltage as 0 if it is open circuit then how can we say capacitor cannot charge in the observation point 2 of voltage doubler
I guess there should be something wrong wrt that circuit cz if we suppose capacitor is some sort of open circuit stuff(there is no current through the capacitor) and we replace the capacitor with some sort of switch that is off, we won't get the input voltage at the output side.
At 55:14 the input voltage goes from -V0 to +V0. But C1 is already charged to V0 and in series with the supply voltage. Why then do we not have 2V0+1V0 to give 3V0 out ?????? Can anyone explain this. Or at least 3V0/2 Thanks Mike
D1 is off when AC changes from -V0 to +V0. But the condition to turn on D2 has changed. The initial state of C2 has no charge and, hence, D2 is on immediately after -V0. And you get V0 increase at the output. But when AC changes from -V0 to +V0 at the 2nd time, D2 already has +V0 at cathode. D2 won't turn on until AC has increased from -V0 to 0. That is, C2 only gets charged when AC changes from 0 to +V0. Per capacitor attenuation, the voltage of C2 will increase V0/2. Repeat the previous steps, you will find the voltage of C2 increases V0/4 for the next AC cycle. That's how voltage steps up on C2 to output +2V0 finally.
@@yihou6433 you missed one thing in the first -V0 to +V0 phase. there's already V0 voltage in C1, in previous example, Vout goes to 2V0 because of that. Here, Vout won't be 2V0 since some voltage should go in C2, which makes (1+1/2)V0 a possible answer( some voltage in C1 release into C2). So i think there's something wrong in the video here. Apart from this, the future behavior of Vout is understandable.
He is considering the possibility(Please keep this in mind that this might not be what actually happens) that Vout stays constant, for that to happen with Vin going down, the capacitor must loose charge, as the voltage across the capacitor is (Vin-Vout) (Vin is going down, Vout is constant). Now, a capacitor loosing charge is practically the same as the capacitor discharging.
hey sir , thank u for providing us best of ur knowledge of electronics bt sir in this lecture at 1 hr 1 min 45 sec u have drawn the in/p and o/p characterstics in that i have a doubt or u can say acc to what i learned from ur lecture is that the vout must be constant till completion of 2nd neg cycle ends and when 2nd pos cycle starts then d1 becomes open d2 become short and then we obtain vout =v0/2 pls correct me if im wrong, if not then also pls clear the point in comment or through any video .. pls sir
as the vin is more negative on upperside of circuit that means lower side of circuit has to be more positive (as by KVL total current across the circuit has to be zero so more -ve + more +ve = zero) so positive current going onto the anode of D2 so D2 is turned ON.
@59 when d1 is on then c1 gets charged to vo (reverse polarity)then after d1 gets off then also d2 remains off as voltage at point A not higher than the vout(which =vo) it should remain as it (vout = vo) till 3rd postive cycle then it should charge to get increment of vo/2. Am i right ? Here .. Anyone who follows the same as i am ?
Virat Mishra The diode didn't turn on. it just turn off (why we we are decreasing input voltage so the circuit now open circuit) what ever input voltage is output voltage no current flowing through diode so that no voltage drop But he said 54:24 diode turns on -Vo to 0 how it possible?? that's my doubt
For the diode to turn ON, its anode has to be "more positive" with respect to its cathode, which makes conventional current flow possible from anode to cathode. Now look closely at the circuit, since input is changing from -Vo to 0, cathode of D1 is trying to increase with respect to anode. For this to happen the current must start flowing from cathode to anode, which, is not possible in case of a diode. Hence the diode shuts off. Hope this helps.
During the first half cycle that sir is neglecting for easy understanding of the voltage doubler circuit, capacitors c1 and c2 obtain some charge because d1 is off but d2 is on. This way, the voltage at output should not be zero at the start of 2nd half wave. If I'm wrong, someone please explain the reason for vo=0 in quarter part of 2nd half.
He is not ignoring the first half cycle, he just isnt using it as the starting point. Imagine that at the very beginning the first thing to go into the circuit was the sine wave going negative. To analyze the circuit we can start at any point that we would like and he just chose that point because we had seen something similar to that previously in the lecture with the single diode single capacitor.
at min 27 Prof Razavi said that if we have a variable voltage source connected with cap then the cap in not connected to any thing that the o/p voltage is the same as the i/p voltage as KVL said in lec 10 at min 29 he said that we can not determine the o/p voltage if we have zero current in an infinite resistance i really get confused please help :)
he said as the circuit is open so there will be no current to charge the capacitor and eventually the voltage across the capacitor will be 0 and the input voltage will be equal to the output voltage according to the KVL
