RISC-V Logisim Register File 

Learn about the RISC-V instruction set architecture by building hardware. In this video, I use Logisim to build a 32-bit register file that will eventually be incorporated into an RV32I CPU that can be synthesized on to an FPGA.
There are a number of resources that I recommend you study as you go on this journey with me:
RISC-V Green Sheet: inst.eecs.berk...
Design of the RISC-V Instruction Set Architecture: digitalassets....
Great Ideas in Computer Architecture (week 2 and 4): inst.eecs.berk...
Other helpful resources:
Online RISC-V assembler: riscvasm.lucas...
Logisim Evolution: github.com/log...