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RiscV Logisim Load Datapath

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Learn about the RISC-V instruction set architecture by building hardware. In this video, I add load instructions to the datapath in order to load bytes, half words, and words into the register file.
I highly recommend you watch the videos on this playlist to this point as I use many of the modules built to date:
• RISC-V Logisim Program...
There are a number of resources that I recommend you study as you go on this journey with me:
Github for Python Source: github.com/chu...
RISC-V Reference Card: www.cs.sfu.ca/...
Design of the RISC-V Instruction Set Architecture: digitalassets....
Great Ideas in Computer Architecture (week 2 and 4): inst.eecs.berk...
RISC-V Specification: riscv.org/wp-c...
Truth Table: docs.google.co...
Other helpful resources:
Online RISC-V assembler: riscvasm.lucas...
Logisim Evolution: github.com/log...

Опубликовано:

29 авг 2024

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Комментарии : 3

@rjones8508 2 месяца назад

In load byte should the selected byte reflect the default little Indian integer format (count bytes from the right)? Also, instead of all the shift mechanics, can one of 4 byte mixes be used instead?

@chuckbenedict7235 2 месяца назад

I assumed that words are stored big endian in RAM. The spec says it can be done either way. It's easier to demo imho. Regarding use of mux for byte extraction...interesting. How would you propose? My hw implementation was based on me writing some pseudo code (which I did off camera), and shifting is what I envisioned.

@rjones8508 2 месяца назад

Maybe 8 4-bit muxes with the 1st mux inputs on input b0,b8,b16,b24 outputting to b0, 2nd on b1,b9,b17,b25 outputting to b1 etc. The 2 bit selects are common to all 8 muxes. I think its the same or similar technique you used for the half word but not sure. The mux effectively performs the 0,8,16 or 24 bit byte shift depending on the select.