I study at IIT and I can safely say that this guy explains the subject better than any of the professors here. You are doing a very good job man...a huge respect for you.
I've learned all of the concepts in my Logic Design class from this guy's videos. Most of the college professors I have had should be fired and guys like this should be hired and given a high salary.
Huge respect and gratitude to Neso Academy and the tutor. You teach every little detail with great clarity and logic, thank you sir. Please keep doing this videos.
This channel is a gold mine. You restore my faith in this world. Channels like this don't just help students, they do what universities should. They focus on the spreading of knowledge. I can tell that that you know and love this subject and I'm proud to call myself your student. Your on the others side of the planet and you've taught me more than my professors have in person.
I am just amazed to see how u r presenting such a quality education for the entire DLD course just for free..I could jst literally sit for hours and complete all ur lectures just 1 week before exam..Thank you so much for the hard work sir...
oh you are a great Profesor ..... You deserve money for this. Soo helpfull... and really help me understanding this crazy thing. And now its not a crazy things anymore. I'm even looks like a profesor when I explain this in on my presentation in my class because I learn this from you.
i compared this video with all the other videos in youtube fr the same topic n gosh! no one cud explain in an elegant and simpler way than you...keep up the good work cheers thanks
@@darshanjaviya4770 yes I beleive so too, why flip S and R in the case of NAND gates? a high on the input S should always set Q to high, no matter which gates are used. S means "Set".
Dude first of all thanks for the video. I have a doubt, just after when you change the values of S and R after giving them 0 and 1 or 1 and 0... i.e., when you make both 0 why doesn't the values of Q and Qbar change, why does they remain same. I mean how did you make out that "previously Q is 1, input for one of Qbar is 1 so it will be 0". Also dude what happens when initially both are 0? Please reply
There is two important things that u don't mention Fast : the time that the gate will take in 11 state is different from gate to gate that will do the unused state . The faster gate in response will be one and the other will be zero 2- there is an error in presentation the RS latch with nand gate U have to correct # inverter the R and S before gating to nand (use not gate ) and correct the truth table Thanks neso for every thing Thanks from Egypt ♥️♥️
Thank you so much for this wonderful explanation. It's was very useful for me. Because of this lockdown our lecturer couldn't complete this chapter and this topic was really new for me. And I have exams in two days. Tysm for this video. 😊
my simple question is that for the forbidden state why can't we consider both the case simultaneously at the same time? why do i have to calculate either q or q' first?
at 10:45, in case 2 when you set the value of s and r you take the output from Q compliment but in case 3 when you set the value of s and r you take the output from Q, this is doubt that when we came to know that after setting the value of s and r which output we have to take first Q or Q compliment ???
Sir I can see that from the truth tables you used active high for the Configuration with nor gates and active low with the configuration with nand gates. Why? Are they equivalent ? Or what? I don’t understand
Well the same thing will happen in the initial setup when both inputs are zero,when we set up the circuit, as in case 3. So... again we will have 2 different states with same configuration.
I have a conceptual doubt about Flip - Flop, Whenever we use S - R Latch using NAND gate then we use S in the I/P of Q and R in the I/P of Q'. But in the case of NOR gate, we use R in the I/P of Q and S in the I/P of Q'. NAND me, jab Reset = 1 ho raha hai tab Qn = 1 ho raha hai and jab Set = 1 ho raha hai tab Qn = 0 ho raha hai, jab ki ye NOR gate me sahi se O/P de raha hai Jabki agar hum NAND gate ke S-R FF me bhi NOR gate ke tarha hi S and R ka I/P de to same hi kaam kar raha hai like NOR gate in case of S = 0, R = 1 and S = 1, R = 0 Then why are we flipping the I/P? I mean NAND and NOR both S - R Latch me hi agar hum S and R ka same hi orientation rakhe to in both case jab Set = 1 hoga then Qn = 1 hoga and jab Reset = 1 hoga then Qn = 0 hoga jo ki meaningful bhi banta hai...
in nand gate when you have s = 1 ( set ) , you get Q = 0 ...so what was the point of reversing the inputs and getting reverse outputs, instead of just letting it work the normal way ? Edit: Actually, S and R in nand gates are S' and R' ( inverted )
I need a teacher like in my school. the one I have is constantly screaming and swearing and all students get low marks.. anyway thanks for sharing this.
We observed Q orQ' as 1or 0 first and depends upon it we will thinking the next output so....Is it not memory? I mean when R=0 & S=1 so in respect to S, Q' is 0 (according to nor gate)and then it goes to the R then both 0 &0 makes the output Q is 1. So as we gave the first input in S or R and we consider one output according to nor gate why?
I got the truth table correct for sr latch using nand gate, but you said S means set so, when we give s=1 we should get Q as 1 in nand form no, why we would get 0? And why S and R inputs are reversed in NOR configuration compared to NAND? Is there any reason for reversing inputs, truth table outputs between NAND and NOR configuration?
