Finally, this is Amazing!! Awhile back (20+ years ago), I was slaving out designing custom ASICs , SDR, VCSELs, and did clocked-down simulations using FPGAs. Our design flow tools that we used were in millions!! Cadence tools, Mentor tools, Xilinx, Lattice, Altera, co-ver c/c++, VHDL, Verilog, SystemVerilog, HyperLynx, etc... whatever is state-of-the-art tools and the leading edge tech , we used them!! 😅 Aspiring engineers and die hard hobbyists: Dive in, take advantage because this is not easy to make available
Back around 1980 I wanted to go on ( the British ) TV Show "Jim'll Fix It" and get my own custom made IC made in a silicon fab. It was only after that I learned that ( at the time ) custom ICs cost hundreds of millions to make! It seems Moore's Law has also worked with the cost of ICs
Swiss watch manufacturers have their own around 130nm fab lines. Small image sensor manufacturers have their fab lines (tough business and a few may struggle. If their existing process is suitable, then a deal might be to the advantage of their bottom line. But everything is going to be highly tuned to their image sensor's performance, no exception, so you might find compromises in circuit performance compared to normal 130nm processes). Of course, back alley Chinese cheap chip makers, using old foundry equipment.
Thats very interesting, what use do watchmakers have for semiconductor fabs? I cant think of anything apart from maybe quartz watch IC's, but I feel like it would be easier to let someone else make them rather than build fab capacity.
And when you have to submit 20-30 times to get your modestly complex design to work to a proper degree? I know people in the industry, a top chip designer. At 130nm, you should be able to get the chip working in GHz (high energy performance design) not up to 50mhz. At low energy design they get over 600mhz. They are trying to get a charity off the ground to teach chip design at highschool using a lower cost one micron fab machine. I think universities are included. There are new etch and dip machines a fraction of the costs of old machines, which makes your 160x100 tile a lot cheaper, and likely able to go smaller faster and lower energy, compared to 130nm. I'll post another comment on other sources of 130nm fabs you might like to check into for a better deal for your service.
There's a lot involved. An open source flow from start to end is perfect for education, because the tool install is easier and students don't need to sign an NDA. But there's only 1 open source PDK that we can buy MPW runs on.
@@ZeroToASICcourse Interesting. They are proposing a about 1micron 3D chip printer, and gave their own tiling chip design tool, which the original version was around 3-6 kilobytes on a 386. Contact printing is available out there for small sizes, so 3D printing at sizes similar to the ones you use should be possible one day. So, 3D chip, strip and wafer printing, should be possible. Which means people get to readily make their own chips on a bench or desktop. 130nm would solve most low to medium speed applications. With 1-6ghz, most remaining high speed applications.
@@ZeroToASICcourse There are companies doing electron beam lithology, which you could get people together to go something pretty unique. Electron beams have accuracy smaller than atoms. I had proposal to do this higher speed, but too sick to get into it, but there is company who seems to be doing some mass production technique. Atomic semi, or something. It's the kid who was doing chips in his parents garage, got together with one of the top chip designers who had been doing AMD's later chip, and did the top end Alpha processor at DEC, has hot tougher with him to start this company, to do really top end cryptology chips. Maybe you could get a free open source run as a marketing effort. You could do something really special with that at atom sizes, and ask for a little slither of wasted space on each wafer, to experiment with, say 1mm2 to 1cm2 on each wafer, what ever little area is left over they can't fit another chip into. At atomic levels you can fit many tiny chips. The minimal instruction set forth processor designs are 1000 transistors plus. There are many iorm source soft core fpga designs (more than all the other computer language processor designs combined by far). The trick to get it to run at the high speeds possible at less then 1nm, is to combine it with full SRAM address space, and only have IO streams coming off chip, and there are certain Thz ways of doing processing chips. Imagine a 16 bit processor with 128KB memory to do digital signaling processing work flows, but don't know if sram can get anywhere near that speed, but these alternative processing technology is likely suitable to make a faster memory than standard SRAM, and have near zero leakage, which reduces heat a lot, with near perfect efficiency. Some people will probably know the technology I am talking about. The research is talking about 4Thz (I had wanted to do it myself years ago, and they seem to have similar enhancements to what I had been hoping to try. There is another related technology that is talking about 40Thz, which is similar to what I wanted to do decades ago, but now we are realising a way to do atom sized circuits and the technique, to maximize this speed. Again, it's a matter of even more localisation of memory to maximise speed, and you have to go to more complex circuits to minimise access to the on chip memory, to allow it to work at higher speed more often. You can 3D stack circuits with the previous technology, but it will still accumulate some heat minimising the number of layers which can be stacked, but stacking will localise memory and processing density a lot more. So, 32bits+ with a full memory are desirable. If you are interested, let me know, I can get people who would want to do this. The additional problem you get is how to split chips off in the micro plus scale in size. The answer is that the electron beam is probably able to do that by design. I have ideas for that from the past. Having beaten down the fungal infection in my brain I may no longer be able to do this, but can remember a few things. Apart from that, with forth processors, there is a group a person I have talked with is working on software for, who have a 40 core 6Ghz chip that is 1-2mm2, and extremely low energy for today, which is probably (the details are secret, but I know the sort of fab tech they are likely using). The misc community holds the world record for lowest energy actual processor chip for many years (but it is primitive, low energy version at 130nm, and not the sort of design I had needed). I will have to look up what was said, but sound like it could be easily cooled with an effective 240Ghz of combined bandwidth, but is in the zone of my proposed designs many years ago. This technology then would be many times slower than that I mentioned above, and those are just the tip of the iceberg of what I was looking at, but these are available and ready to experiment with. The other thing is how to power, but that's possible. Anyway, I'm fairly dizzy and have to leave it at that. But, a full high end PC in the volume of a coarse grain of sand, including storage, is what we are looking at, but I wouldn't guarantee we could cool that, on the efficient technique.
@@ZeroToASICcourse Okay, thank you! I hope, that is going to change at some point in the future, since i would really like obtaining more than one. The cost for producing, (let's say ten times) more chips is probably not that of an issue... One on the Demoboard, nine without would be great!
@@teejay872 In my opinion a single chip is really really useful already but the ability to order more than that would be even better. Especially since having the triple amount produced would surely not even close to double the total cost...
I know guys interested in making chips. What are the prospects for commercial production? They can fit a highly efficient speedy processor in 1000 logic cells. There a maybe a dozen of there type of FPGA soft cores. Some fit in 150-300 luts. I'm sure a few people would be interested if they could progress on to a realistic commercial production deal of 1000-100,000 (though very small compared to big players who do chips 10,000,000- 100,000,000+). What about a modern 45nm low energy process deal?
