Learn how to design your own computer chips! The Zero to ASIC course covers everything you need to design your own chip using the open source tools. You can even get it manufactured into a real chip!
Finally, this is Amazing!! Awhile back (20+ years ago), I was slaving out designing custom ASICs , SDR, VCSELs, and did clocked-down simulations using FPGAs. Our design flow tools that we used were in millions!! Cadence tools, Mentor tools, Xilinx, Lattice, Altera, co-ver c/c++, VHDL, Verilog, SystemVerilog, HyperLynx, etc... whatever is state-of-the-art tools and the leading edge tech , we used them!! 😅 Aspiring engineers and die hard hobbyists: Dive in, take advantage because this is not easy to make available
Hi, I'm about to start my masters in Robotics/Ai (hopefully going into a PhD) and I'm interested in analogue chips for Ai. So that something that's covered on the course?
@@ZeroToASICcourse many thanks , I managed to build a vm using Ubuntu which took 4 full days , so I will definitely check out the link and the course 👍
I’ve installed xschem and ngspice and I get errors when running ngspice after netlisting. The issue is that there is a “.save i(v1)” in my spice netlist that ngspice doesn’t like. Any ideas how to stop xschem spitting this out. My sch has no commands that would do this and I followed Stephans tutorial to the letter. Just curious if anyone here has experience this. I’ve spend over a day trying to figure this out. Rebuilt both tools and used different repos. Same result.
BTW if I hand edit the netlist spice file and remove the .save i(v1) it works fine. However I don’t want to be editing this file every time a netlist changes and I want to simulate. PITA
@@ZeroToASICcourse No. So as it turns out the VSource symbol by default has a “.save (@v)” attribute in it and this gets dumped into the netlist. The other Voltage Source symbols don’t have this. I’ve done a load of SPICE stuff in the past and wasn’t expecting a released symbol to have this in. I suspect Stephan was doing an experiment and it got accidentally checked in.
It’s a “.save. ….something attribute”. Can’t recall off hand what exactly it is now since I’m not in front of the tools etc. Descend into the symbol and press “q” on the keyboard to see it. I put a “*” in front of it to comment it out.
So glad I saw this video and glad that you're taking this on, HUGE thank you! This CPU was also very influential on my past also and the news of its discontinuation makes me really really sad. I just went on Mouser and bought a dozen of them, I can't believe how expensive they are. First two computers I had were TRS-80 model I, and ZX81.😥😥
If I enroll in your course a bit late, suppose later this year like November December, will I be getting same time as other for development or will I be asked to complete it sooner? Should I enroll in next batch? Basically when does your batch start and when is the best time to enroll in it? Actually I am from India, will I be getting the test boards?
You can enroll whenever you want. The time it takes to get a board depends when you submit. Take a look here for the dates on previous shuttles: tinytapeout.com/runs/
Bought Ed's book after watching this and am very glad I did - IMO a must-read for anybody, let alone those interested in technology and manufacturing. If only they'd taught us this kind of history in school ;) Thanks for the interview and great book
So surprising that it's only like 1/20th the speed of a real 6502. Long ago I worked on a CDC 160A, which was all discrete germanium PNP transistors and wire runs up to 5 feet long.. It was the size of a door and had a 12 microsecond clock. Slightly faster, and in 1961! I'm also surprised you couldn't find some suitable active complementary pullups, that would have greatly helped the speed and lowered the power drain. For instance the BSS84AK,215 is only 18 cents each, is p-channel, and not too slow. It does have a whopping 18pf of gate capacitance, which is very low for a fet, but may be a problem if you need a lot of fanout.
Perhaps adding some internal memory would be a good way to make use of the extra space? I know that it would not truly be a Z80 replica anymore, but it could be fully compatible. I'm not so keen on the idea of multiple CPU models in one chip, if they can't all run at the same time, it feels like wasted space to me. The attraction for me personally is the idea of a powerful vintage chip that combines memory and other necessary features for a fully operating computer, as long as the assembly instruction set remains compatible and simple to learn and use to build anything you want.
@@ZeroToASICcourse Do you have a complete list of all software that you personally use for ASIC design that is installed on your computer? I am buying a new system for programming and possibly ASIC design so want to do a clean install of all i need in one go, no faffing about going hither and thither. Hopefully sorted out within a month or two. Will be buying your suggested books too. Thanks for the videos!
Let's see: Magic, ngspice, klayout, openlane, icarus verilog, gtkwave, cocotb, sby, gcc. TBH it's not so much the tools as the specific version of each tool. For the course I provide complete install instructions as well as a VM. For OS I recommend Ubuntu 22 LTS. 24 is not ready.
Excellent. Thank you very much. Lovely stuff all of this.
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Note to availability: In the "Eastern block" it was really hard to get any of the computers, but the cheaper ones, especially in the late 80s were available as imported from the West. Sinclair (ZX Spectrum and its variants), Atari (800XL, XE and 130XE) and some others like Commodore, Sharp or MSX weren't that common. Socialist block was able to produce some required components, but only a limited amounts and quality wasn't always that good. There were clones of 8080 (Tesla in CZ), U880D (Eastern Germany Z80 clone, which was not fully compatible), Russian DRAM chips (64Kx1), DRAM 16Kx1 were bit more common. In CZ we had locally produced computers based on 8080 and Z80. We had IQ150 / IQ151 (8080, 32KB RAM, modular with possibility to plug in number of extension modules for better graphics or even networking), PMD85 (Z80 based - I think) and its variants, PP-01 (I have no idea on architecture here) and then several ZX Spectrum clones (Didaktik Gamma, Ondra?). Problem was, they were produced in very small numbers, mostly for schools, so nobody had them at home. I had a ZX Spectrum+2 from the late eighties and I have it till today :-) It was fantastic machine and I absolutely love it.
Open source Z80? What is this project? Like all the designs and specs to build Z80 if you build chips? Sounds amazing. Z80 could be made super small and tiny with modern manufacturing and it's quite a capable CPU. Not everything needs tons of computing power, you can do so many things with it. You don't even need to run a full fledged modern OS on it, just some kind of a small simple scheduler, maybe something like FreeRTOS+Z80 this would be awesome.
The pads in the ChipIgnite are spread out quite a bit. If you pack them together with 10 per side you could have a much smaller area. With pads that are 80µm wide and 200µm deep, 10 per side plus the corners would be 10x80+2x200 = 1.2mm. This would give you a chip area of 1.2² = 1.44mm². The actual usable area inside the pads would be (10x80)² = 640000µm² or 0.64mm².
8-bit chip wars forever! Z80 was my first CPU and I loved it... In retrospect, I wish I had 6502 :) it would've been easier to write assembly for when you are 13 years old ;)
I saw a few Intel 4040 chips in a junk box whilst working at Marconi Research in Chelmsford in 1980. No idea if they ever used it for a real product. They had their own in house 16 bit processor for use in Radar Systems at the time. You did not mention the thousands of computers based on Z80 and running CP/M around that time.
I recently stumbled over an IDE called KliveIde that allows you to write Z80 assembly and inject the compiled code directly into an emulated ZX Spectrum's memory. It was such a cool experience to have a comfortable programming environment for the Speccy, I immediately started writing some 3D stuff using vector graphics. If only I had access to something similar 40 years ago :)
I got a TRS-80 for Christmas when I was 14. Learned Z80 assembler to make copies of the protected "system" cassette tapes. Kicked off a 30 year career in software engineering. Soft spot in my heart for the venerable Z80!
Minor correction, PMOS and NMOS were invented at (roughly) the same time. The reason why CMOS came later was because it required figuring out how to create PMOS and NMOS transistors on the same die.
1) FPGAs don’t handle 5V IO 2) “preservation” efforts to build silicon as close as possible to the original. FPGA in that regard is more like “software emulator of CPU” just faster, it has almost nothing to do with how actual chip worked.
@@rej_aka_renaldas_zioma Disagree. What is on the FPGA is gates, not software. Your 5v I/O makes no sense, 5v I/O is still the standard pin on FPGA. An FPGA can be cycle accurate, and you can even specify it down to individual gates if you want. If, instead, your purpose is to get a cycle accurate Z80, that is not necessary. This would be insertable into any Z80 design, if not package wise. Then again, an FPGA Z80 could host an entire design including the Z80 on that same FPGA, so I would argue more useful in any case. PS you aren't going to be able to get a tinytapeout 40 pin original package, either.
@@scottfranco1962modern FPGAs (like iCE40) are 3.3V I/O tolerant not 5V. If you can point to small FPGA that has 5V IO, please do! It is not that much about being cycle accurate, that is a minimal requirement of course. Ideally I want to arrive to a similar signal delays (sub cycle) and internal chip layout. Why? Absolutely no practical reason except to preserve it for the future. I agree that it is impossible (or close to impossible) to fabricate DIP40 right now. The first attempt will be QFN64 with PCB adaptor to DIP40. Will see how it goes afterwards…
@@rej_aka_renaldas_zioma "modern FPGAs (like iCE40) are 3.3V I/O tolerant not 5V." meaning completely compatible with 5v I/O. You really had to bend over backwards to split that hair. And again, with "signal delays" the original Z80 produced and consumed signals on the clock edge, so you would never see any internal delays on the pins. Further, yes you COULD emulate internal delays if you really wanted to. People can and have specified designs entirely in terms of gates for FPGAs. Verilog will accept gate descriptions. Why you would want to is beyond me. The point here is that you can produce a Z80, with completely compatible external signaling, with an FPGA, if not the exact same package, which was never the stated requirement. Further, its a more useful Z80, since it is an FPGA cell, meaning it could replace the rest of your design as well. Finally, and I hope this nails the coffin shut, the Z80 itself, was not cycle or gate identical as the Z80. How do I know? Because I am ex-Zilog. My boss was the guy who redesigned the Z80 in later products. He replaced the random logic Z80 of the early days with a microcoded Z80. All of the later Z80 products used that core.
Zero to ASIC should provide a certificate or udemy style qualification for anyone who has completed a computer chip design as part of their program 😀. That would look good on your CV/resume.
Having Z80 at ~50Mhz drop-in replacement in DIP40 could be nice, but for 10$ is pricey. Could you put Z80, 6502 and 8088 in one DIP40? That definitely could start to compete. If you could add even few hundreds of bytes optional cache that could become a bestseller for retro-diys!
Yeah, all classic 8-bit CPUs on a single chip is a great idea and I am toying around with it! Certainly not easy though. $10 - that’s a current price for Z80 on Mouser! I was quite shocked too!
@@rej_aka_renaldas_zioma you can still buy used one for a $1. But 8088 even used costs about $10, so from my point of view to guarantee success there must be 8088 on the same die
Drop IX and IY, use those codes for some threaded code jump opcodes, drop the bit test stuff, and just add those to the ED xx opcodes. Make a more useful IM 3 mode and put 64 kB on the die with a serial flash boot load hardware.
Yeah, would be cool if tiles of tiny tapeout could address other tiles. So we could have different CPUs (Z80,6502,RISCV,SH2,ARM2), different GPU (PPU VDP VIC ), and cache (code, data, sprites, wavetables (pcengine)) all spread over the tiles and then mix and match as we boot the chip. I still did not understand the bus here. Atari Jaguar has a single 64 bit bus to connect components on a single die. Quite obviously a lot of these components were originally individual PCBs.
@@ArneChristianRosenfeldtyeah, I was thinking similar, all 8-bit classic CPUs (6502/6800/8080/z80), VDPs (9918/HD6845/VIC/PPU/ULA) and Audio synths (SN/SA/AY/YM/APU) on a single chip! With configurable bus and 128K RAM.
I looked at some of the projects that were on the previous tapeout, and most seem to be smallish learning-experience designs that could easily be done faster and cheaper on an FPGA because they were all-digital (and many FPGAs have real RAM cells instead of consuming logic+flip-flops), but that doesn't give you the full experience of what it takes to do a chip. So, what kinds of designs can you do with 130nm ? To start with, this is not bleeding-edge process technology. 20 years ago I was wrapping-up a 130nm mixed-signal design, and I think we could get a ring oscillator running up to 15Ghz. NMOS, PMOS, and diodes are easy. MOS capacitors were easy, diffusion resistors were a bit tricky to get the exact value you wanted, but what you did end up with was well-matched for nearby resistors with the same dimensions. Poly fuses were tricky because they didn't blow reliably. Spiral inductors were possible, but their inductance was very low. Our process had regular and thick gate-oxide, so we could get some transistors to 1.8V or 2.5V. We had 4 metal layers.
Mixed signal is possible on tiny tapeout. Even before someone made a PLL, whereas on an FPGA the system clock dominates everything. You could reproduce the clock circuit of 6502 or 80386. Maybe someone could tell me why RCA 1802 needs so many real physical cycles for one phantasy machine cycle. With so large features, I bet there could be DRAM like the registers in intel 8080 or VDP in NES.
