thank you for the great insight! I can’t speak to current industry trends, and I will have to agree with you that using an FPGA for this may not be business viable. I’d like to emphasize that the purpose of these shorts is to drum up interest from new-grads, developers, and engineers who have never worked with an FPGA. My hope is that they will find their way to my Verilog tutorials from here.

But there is no doubt that every ASIC chip for video compression was first developed on an FPGA before the foundry could start producing it.

Wholesale compression by streamers like RU-vid usually have proprietary IP, and AMD/Xilinx is definitely a vendor with the Alveo line of neutered mostly FPGAs. They probably have some hard IP to do compression but hanging bits are usually configurable. It just makes more sense

Interesting, I have not heard of this. Who is working on matrix coprocessors?

Theoretically, the next step is to make it out of TTL chips(if you're crazy enough), run software, then ship the logic design to a chip fab (I hear google is doing larger 100/50nm for relatively chip, as long as you make it open source).

@@rya3190 But I thought that the purpose of using an FPGA was so that you wouldn't have to have all those individual logic chips in the first place, but rather you can simply program it into a single FPGA chip. It's what happens after that that I'm asking about. And rather than having a custom chip fabricated, can you keep using an FPGA by ordering a board that has your custom circuitry on it plus the FPGA chip?

@@SDJ41 You should be able to...They probably sell them in chip form. The TTL was more of a joke, I'm pretty sure an FPGA would be faster and not as mind numbing. It's either you keep using the FPGA or get your chip made. If you're just tinkering, it's probably better just to keep the FPGA(s) and make a good circuit board for it/them, but if you're going to sell it, probably better to get the dedicated chip. Takes up less room, cheaper over time, and can't be messed up by customers (more or less...)

@@rya3190 Yes, that's it. I simply wanted to know if PCB order houses were capable of doing this. But I can see it depends on the seriousness of the project and what you're selling. Thanks.

So, heres my recommendation for this. Start very small. Pick up a low spec Lattice FPGA development board for something like an ice40 or something. From there make novel FPGA design you think is fun/cool/educative. It doesn't have to be super complex. Learn KiCAD for PCB design through Chris Gammel (contextual electronics) tutorials. Now the FPGA you choose may have multiple voltages and you might have to sequence those so you'll need to learn how to do that with power sequencing ic's or do it discretely yourself. There's a lot of things to keep in mind when designing a PCB for an FPGA, even if it's a low spec one, but its great fun to learn and you'll feel very accomplished at the end. I hope this is enough to point you in the right direction. Try and do some intermediate circuit projects as well before you tackle a whole custom FPGA solution. But definitely reach for the stars.

the C program writes x number of black pixels and then x number of white pixels, both starting from index zero. this was to test a VGA subsystem i created on the FPGA from scratch (without using intel IP video cores). i never could fix this issue where it was tearing the image over and over at different offsets. so that’s why the video feed looks all crazy.

this is the commitment that makes you a true scientist!

@@metaphysicscomputing​​⁠​⁠​⁠ there is something called a front porch and a back porch when displaying on monitors, this is usually a around 200-1000us depending on many things but basically after the horizontal sync pulse you will have to wait a little bit before anything gets displayed on that row, and this goes for every single row, some people fix this by tricking the code into thinking the monitor is wider than it actually is and this usually easier than creating a buffer before displaying, it looks like the black that is displayed on your screen should actually be in the buffer zone(front and back porch) you would have to figure out how many extra pixels/buffer time solves your specific situation though.

@@metaphysicscomputingtearing because of Vsync

Ti has made some demo Python parser scripts that come packaged with the mmwave SDK. Mine is located in this directory: C:\ti\mmwave_sdk_03_06_02_00-LTS\packages\ti\demo\parser_scripts

altera de2-115

I am a software developer, but the work here on my channel is my hobby

Glad it helped!

I have just started on creating the tutorial! I am planning on making a short guide to get this type of setup and then I am planning to do lots of tutorials based on that.

Same problem as @user-mx8gk6gf2w when I connect up PC running windows 11 OS.

I am currently struggling with the same thing. I am using the provided HDMI reference design from the DE10-Nano CD and I am also using this github repo guide as a reference: github.com/zangman/de10-nano/blob/master/docs/FPGA-SDRAM-Communication_-Introduction.md I am still debugging the code I wrote to scale up the design from github to write RGB pixel data for a 1080p picture.

@@metaphysicscomputing I can now using the mmap function to read or write data to HPS DDR on HPS side . Next, I will study how to send video data into HPS DDR through mSGDMA on the FPGA side, my video data is generated on the FPGA side.

@@jajjajajj Nice! 😁 I also got the SDRAM controller to work for my own Avalon MM Master. I’m now debugging my FPGA implementation to display the frame stored in the DDR3.